In this talk we present dataflow analysis techniques that are used to compute scheduler settings and buffer capacities for our multiprocessor system with caches and shared external SDRAM memory. The computed settings are such that throughput and latency requirements are met for a given set of input streams. In our system we regulate service instead of traffic. This is because it can occur that the execution time of a task exceeds the worst case execution time estimate that is used at design-time.

CV Marco Bekooij:
Marco Bekooij received a M.S.E.E. degree from Twente University of Technology in 1995 and a Ph.D. degree from the Eindhoven University of Technology in 2004. He is currently a senior researcher at NXP Semiconductors. He has been involved in the design of a channel decoder IC for digital audio broadcasting and he developed a constraint analysis based scheduler for VLIW processors with distributed register files. This scheduler has been productized by the start-up Silicon Hive. Marco's current research interests include the design and analysis of predictable embedded multiprocessor systems.