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stm32f10x_map.h
1 /******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
2 * File Name : stm32f10x_map.h
3 * Author : MCD Application Team
4 * Version : V2.0.3
5 * Date : 09/22/2008
6 * Description : This file contains all the peripheral register's definitions,
7 * bits definitions and memory mapping.
8 ********************************************************************************
9 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
10 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
11 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
12 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
13 * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
14 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
15 *******************************************************************************/
16 
17 /* Define to prevent recursive inclusion -------------------------------------*/
18 #ifndef __STM32F10x_MAP_H
19 #define __STM32F10x_MAP_H
20 
21 #ifndef EXT
22  #define EXT extern
23 #endif /* EXT */
24 
25 /* Includes ------------------------------------------------------------------*/
26 #include "stm32f10x_conf.h"
27 #include "stm32f10x_type.h"
28 #include "cortexm3_macro.h"
29 
30 /* Exported types ------------------------------------------------------------*/
31 /******************************************************************************/
32 /* Peripheral registers structures */
33 /******************************************************************************/
34 
35 /*------------------------ Analog to Digital Converter -----------------------*/
36 typedef struct
37 {
38  vu32 SR;
39  vu32 CR1;
40  vu32 CR2;
41  vu32 SMPR1;
42  vu32 SMPR2;
43  vu32 JOFR1;
44  vu32 JOFR2;
45  vu32 JOFR3;
46  vu32 JOFR4;
47  vu32 HTR;
48  vu32 LTR;
49  vu32 SQR1;
50  vu32 SQR2;
51  vu32 SQR3;
52  vu32 JSQR;
53  vu32 JDR1;
54  vu32 JDR2;
55  vu32 JDR3;
56  vu32 JDR4;
57  vu32 DR;
58 } ADC_TypeDef;
59 
60 /*------------------------ Backup Registers ----------------------------------*/
61 typedef struct
62 {
63  u32 RESERVED0;
64  vu16 DR1;
65  u16 RESERVED1;
66  vu16 DR2;
67  u16 RESERVED2;
68  vu16 DR3;
69  u16 RESERVED3;
70  vu16 DR4;
71  u16 RESERVED4;
72  vu16 DR5;
73  u16 RESERVED5;
74  vu16 DR6;
75  u16 RESERVED6;
76  vu16 DR7;
77  u16 RESERVED7;
78  vu16 DR8;
79  u16 RESERVED8;
80  vu16 DR9;
81  u16 RESERVED9;
82  vu16 DR10;
83  u16 RESERVED10;
84  vu16 RTCCR;
85  u16 RESERVED11;
86  vu16 CR;
87  u16 RESERVED12;
88  vu16 CSR;
89  u16 RESERVED13[5];
90  vu16 DR11;
91  u16 RESERVED14;
92  vu16 DR12;
93  u16 RESERVED15;
94  vu16 DR13;
95  u16 RESERVED16;
96  vu16 DR14;
97  u16 RESERVED17;
98  vu16 DR15;
99  u16 RESERVED18;
100  vu16 DR16;
101  u16 RESERVED19;
102  vu16 DR17;
103  u16 RESERVED20;
104  vu16 DR18;
105  u16 RESERVED21;
106  vu16 DR19;
107  u16 RESERVED22;
108  vu16 DR20;
109  u16 RESERVED23;
110  vu16 DR21;
111  u16 RESERVED24;
112  vu16 DR22;
113  u16 RESERVED25;
114  vu16 DR23;
115  u16 RESERVED26;
116  vu16 DR24;
117  u16 RESERVED27;
118  vu16 DR25;
119  u16 RESERVED28;
120  vu16 DR26;
121  u16 RESERVED29;
122  vu16 DR27;
123  u16 RESERVED30;
124  vu16 DR28;
125  u16 RESERVED31;
126  vu16 DR29;
127  u16 RESERVED32;
128  vu16 DR30;
129  u16 RESERVED33;
130  vu16 DR31;
131  u16 RESERVED34;
132  vu16 DR32;
133  u16 RESERVED35;
134  vu16 DR33;
135  u16 RESERVED36;
136  vu16 DR34;
137  u16 RESERVED37;
138  vu16 DR35;
139  u16 RESERVED38;
140  vu16 DR36;
141  u16 RESERVED39;
142  vu16 DR37;
143  u16 RESERVED40;
144  vu16 DR38;
145  u16 RESERVED41;
146  vu16 DR39;
147  u16 RESERVED42;
148  vu16 DR40;
149  u16 RESERVED43;
150  vu16 DR41;
151  u16 RESERVED44;
152  vu16 DR42;
153  u16 RESERVED45;
154 } BKP_TypeDef;
155 
156 /*------------------------ Controller Area Network ---------------------------*/
157 typedef struct
158 {
159  vu32 TIR;
160  vu32 TDTR;
161  vu32 TDLR;
162  vu32 TDHR;
163 } CAN_TxMailBox_TypeDef;
164 
165 typedef struct
166 {
167  vu32 RIR;
168  vu32 RDTR;
169  vu32 RDLR;
170  vu32 RDHR;
171 } CAN_FIFOMailBox_TypeDef;
172 
173 typedef struct
174 {
175  vu32 FR1;
176  vu32 FR2;
177 } CAN_FilterRegister_TypeDef;
178 
179 typedef struct
180 {
181  vu32 MCR;
182  vu32 MSR;
183  vu32 TSR;
184  vu32 RF0R;
185  vu32 RF1R;
186  vu32 IER;
187  vu32 ESR;
188  vu32 BTR;
189  u32 RESERVED0[88];
190  CAN_TxMailBox_TypeDef sTxMailBox[3];
191  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
192  u32 RESERVED1[12];
193  vu32 FMR;
194  vu32 FM1R;
195  u32 RESERVED2;
196  vu32 FS1R;
197  u32 RESERVED3;
198  vu32 FFA1R;
199  u32 RESERVED4;
200  vu32 FA1R;
201  u32 RESERVED5[8];
202  CAN_FilterRegister_TypeDef sFilterRegister[14];
203 } CAN_TypeDef;
204 
205 /*------------------------ CRC calculation unit ------------------------------*/
206 typedef struct
207 {
208  vu32 DR;
209  vu8 IDR;
210  u8 RESERVED0;
211  u16 RESERVED1;
212  vu32 CR;
213 } CRC_TypeDef;
214 
215 
216 /*------------------------ Digital to Analog Converter -----------------------*/
217 typedef struct
218 {
219  vu32 CR;
220  vu32 SWTRIGR;
221  vu32 DHR12R1;
222  vu32 DHR12L1;
223  vu32 DHR8R1;
224  vu32 DHR12R2;
225  vu32 DHR12L2;
226  vu32 DHR8R2;
227  vu32 DHR12RD;
228  vu32 DHR12LD;
229  vu32 DHR8RD;
230  vu32 DOR1;
231  vu32 DOR2;
232 } DAC_TypeDef;
233 
234 /*------------------------ Debug MCU -----------------------------------------*/
235 typedef struct
236 {
237  vu32 IDCODE;
238  vu32 CR;
239 }DBGMCU_TypeDef;
240 
241 /*------------------------ DMA Controller ------------------------------------*/
242 typedef struct
243 {
244  vu32 CCR;
245  vu32 CNDTR;
246  vu32 CPAR;
247  vu32 CMAR;
248 } DMA_Channel_TypeDef;
249 
250 typedef struct
251 {
252  vu32 ISR;
253  vu32 IFCR;
254 } DMA_TypeDef;
255 
256 /*------------------------ External Interrupt/Event Controller ---------------*/
257 typedef struct
258 {
259  vu32 IMR;
260  vu32 EMR;
261  vu32 RTSR;
262  vu32 FTSR;
263  vu32 SWIER;
264  vu32 PR;
265 } EXTI_TypeDef;
266 
267 /*------------------------ FLASH and Option Bytes Registers ------------------*/
268 typedef struct
269 {
270  vu32 ACR;
271  vu32 KEYR;
272  vu32 OPTKEYR;
273  vu32 SR;
274  vu32 CR;
275  vu32 AR;
276  vu32 RESERVED;
277  vu32 OBR;
278  vu32 WRPR;
279 } FLASH_TypeDef;
280 
281 typedef struct
282 {
283  vu16 RDP;
284  vu16 USER;
285  vu16 Data0;
286  vu16 Data1;
287  vu16 WRP0;
288  vu16 WRP1;
289  vu16 WRP2;
290  vu16 WRP3;
291 } OB_TypeDef;
292 
293 /*------------------------ Flexible Static Memory Controller -----------------*/
294 typedef struct
295 {
296  vu32 BTCR[8];
297 } FSMC_Bank1_TypeDef;
298 
299 typedef struct
300 {
301  vu32 BWTR[7];
302 } FSMC_Bank1E_TypeDef;
303 
304 typedef struct
305 {
306  vu32 PCR2;
307  vu32 SR2;
308  vu32 PMEM2;
309  vu32 PATT2;
310  u32 RESERVED0;
311  vu32 ECCR2;
312 } FSMC_Bank2_TypeDef;
313 
314 typedef struct
315 {
316  vu32 PCR3;
317  vu32 SR3;
318  vu32 PMEM3;
319  vu32 PATT3;
320  u32 RESERVED0;
321  vu32 ECCR3;
322 } FSMC_Bank3_TypeDef;
323 
324 typedef struct
325 {
326  vu32 PCR4;
327  vu32 SR4;
328  vu32 PMEM4;
329  vu32 PATT4;
330  vu32 PIO4;
331 } FSMC_Bank4_TypeDef;
332 
333 /*------------------------ General Purpose and Alternate Function IO ---------*/
334 typedef struct
335 {
336  vu32 CRL;
337  vu32 CRH;
338  vu32 IDR;
339  vu32 ODR;
340  vu32 BSRR;
341  vu32 BRR;
342  vu32 LCKR;
343 } GPIO_TypeDef;
344 
345 typedef struct
346 {
347  vu32 EVCR;
348  vu32 MAPR;
349  vu32 EXTICR[4];
350 } AFIO_TypeDef;
351 
352 /*------------------------ Inter-integrated Circuit Interface ----------------*/
353 typedef struct
354 {
355  vu16 CR1;
356  u16 RESERVED0;
357  vu16 CR2;
358  u16 RESERVED1;
359  vu16 OAR1;
360  u16 RESERVED2;
361  vu16 OAR2;
362  u16 RESERVED3;
363  vu16 DR;
364  u16 RESERVED4;
365  vu16 SR1;
366  u16 RESERVED5;
367  vu16 SR2;
368  u16 RESERVED6;
369  vu16 CCR;
370  u16 RESERVED7;
371  vu16 TRISE;
372  u16 RESERVED8;
373 } I2C_TypeDef;
374 
375 /*------------------------ Independent WATCHDOG ------------------------------*/
376 typedef struct
377 {
378  vu32 KR;
379  vu32 PR;
380  vu32 RLR;
381  vu32 SR;
382 } IWDG_TypeDef;
383 
384 /*------------------------ Nested Vectored Interrupt Controller --------------*/
385 typedef struct
386 {
387  vu32 ISER[2];
388  u32 RESERVED0[30];
389  vu32 ICER[2];
390  u32 RSERVED1[30];
391  vu32 ISPR[2];
392  u32 RESERVED2[30];
393  vu32 ICPR[2];
394  u32 RESERVED3[30];
395  vu32 IABR[2];
396  u32 RESERVED4[62];
397  vu32 IPR[15];
398 } NVIC_TypeDef;
399 
400 typedef struct
401 {
402  vuc32 CPUID;
403  vu32 ICSR;
404  vu32 VTOR;
405  vu32 AIRCR;
406  vu32 SCR;
407  vu32 CCR;
408  vu32 SHPR[3];
409  vu32 SHCSR;
410  vu32 CFSR;
411  vu32 HFSR;
412  vu32 DFSR;
413  vu32 MMFAR;
414  vu32 BFAR;
415  vu32 AFSR;
416 } SCB_TypeDef;
417 
418 /*------------------------ Power Control -------------------------------------*/
419 typedef struct
420 {
421  vu32 CR;
422  vu32 CSR;
423 } PWR_TypeDef;
424 
425 /*------------------------ Reset and Clock Control ---------------------------*/
426 typedef struct
427 {
428  vu32 CR;
429  vu32 CFGR;
430  vu32 CIR;
431  vu32 APB2RSTR;
432  vu32 APB1RSTR;
433  vu32 AHBENR;
434  vu32 APB2ENR;
435  vu32 APB1ENR;
436  vu32 BDCR;
437  vu32 CSR;
438 } RCC_TypeDef;
439 
440 /*------------------------ Real-Time Clock -----------------------------------*/
441 typedef struct
442 {
443  vu16 CRH;
444  u16 RESERVED0;
445  vu16 CRL;
446  u16 RESERVED1;
447  vu16 PRLH;
448  u16 RESERVED2;
449  vu16 PRLL;
450  u16 RESERVED3;
451  vu16 DIVH;
452  u16 RESERVED4;
453  vu16 DIVL;
454  u16 RESERVED5;
455  vu16 CNTH;
456  u16 RESERVED6;
457  vu16 CNTL;
458  u16 RESERVED7;
459  vu16 ALRH;
460  u16 RESERVED8;
461  vu16 ALRL;
462  u16 RESERVED9;
463 } RTC_TypeDef;
464 
465 /*------------------------ SD host Interface ---------------------------------*/
466 typedef struct
467 {
468  vu32 POWER;
469  vu32 CLKCR;
470  vu32 ARG;
471  vu32 CMD;
472  vuc32 RESPCMD;
473  vuc32 RESP1;
474  vuc32 RESP2;
475  vuc32 RESP3;
476  vuc32 RESP4;
477  vu32 DTIMER;
478  vu32 DLEN;
479  vu32 DCTRL;
480  vuc32 DCOUNT;
481  vuc32 STA;
482  vu32 ICR;
483  vu32 MASK;
484  u32 RESERVED0[2];
485  vuc32 FIFOCNT;
486  u32 RESERVED1[13];
487  vu32 FIFO;
488 } SDIO_TypeDef;
489 
490 /*------------------------ Serial Peripheral Interface -----------------------*/
491 typedef struct
492 {
493  vu16 CR1;
494  u16 RESERVED0;
495  vu16 CR2;
496  u16 RESERVED1;
497  vu16 SR;
498  u16 RESERVED2;
499  vu16 DR;
500  u16 RESERVED3;
501  vu16 CRCPR;
502  u16 RESERVED4;
503  vu16 RXCRCR;
504  u16 RESERVED5;
505  vu16 TXCRCR;
506  u16 RESERVED6;
507  vu16 I2SCFGR;
508  u16 RESERVED7;
509  vu16 I2SPR;
510  u16 RESERVED8;
511 } SPI_TypeDef;
512 
513 /*------------------------ SystemTick ----------------------------------------*/
514 typedef struct
515 {
516  vu32 CTRL;
517  vu32 LOAD;
518  vu32 VAL;
519  vuc32 CALIB;
520 } SysTick_TypeDef;
521 
522 /*------------------------ TIM -----------------------------------------------*/
523 typedef struct
524 {
525  vu16 CR1;
526  u16 RESERVED0;
527  vu16 CR2;
528  u16 RESERVED1;
529  vu16 SMCR;
530  u16 RESERVED2;
531  vu16 DIER;
532  u16 RESERVED3;
533  vu16 SR;
534  u16 RESERVED4;
535  vu16 EGR;
536  u16 RESERVED5;
537  vu16 CCMR1;
538  u16 RESERVED6;
539  vu16 CCMR2;
540  u16 RESERVED7;
541  vu16 CCER;
542  u16 RESERVED8;
543  vu16 CNT;
544  u16 RESERVED9;
545  vu16 PSC;
546  u16 RESERVED10;
547  vu16 ARR;
548  u16 RESERVED11;
549  vu16 RCR;
550  u16 RESERVED12;
551  vu16 CCR1;
552  u16 RESERVED13;
553  vu16 CCR2;
554  u16 RESERVED14;
555  vu16 CCR3;
556  u16 RESERVED15;
557  vu16 CCR4;
558  u16 RESERVED16;
559  vu16 BDTR;
560  u16 RESERVED17;
561  vu16 DCR;
562  u16 RESERVED18;
563  vu16 DMAR;
564  u16 RESERVED19;
565 } TIM_TypeDef;
566 
567 /*----------------- Universal Synchronous Asynchronous Receiver Transmitter --*/
568 typedef struct
569 {
570  vu16 SR;
571  u16 RESERVED0;
572  vu16 DR;
573  u16 RESERVED1;
574  vu16 BRR;
575  u16 RESERVED2;
576  vu16 CR1;
577  u16 RESERVED3;
578  vu16 CR2;
579  u16 RESERVED4;
580  vu16 CR3;
581  u16 RESERVED5;
582  vu16 GTPR;
583  u16 RESERVED6;
584 } USART_TypeDef;
585 
586 /*------------------------ Window WATCHDOG -----------------------------------*/
587 typedef struct
588 {
589  vu32 CR;
590  vu32 CFR;
591  vu32 SR;
592 } WWDG_TypeDef;
593 
594 /******************************************************************************/
595 /* Peripheral memory map */
596 /******************************************************************************/
597 /* Peripheral and SRAM base address in the alias region */
598 #define PERIPH_BB_BASE ((u32)0x42000000)
599 #define SRAM_BB_BASE ((u32)0x22000000)
600 
601 /* Peripheral and SRAM base address in the bit-band region */
602 #define SRAM_BASE ((u32)0x20000000)
603 #define PERIPH_BASE ((u32)0x40000000)
604 
605 /* FSMC registers base address */
606 #define FSMC_R_BASE ((u32)0xA0000000)
607 
608 /* Peripheral memory map */
609 #define APB1PERIPH_BASE PERIPH_BASE
610 #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
611 #define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
612 
613 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
614 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
615 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
616 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
617 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
618 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
619 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
620 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
621 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
622 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
623 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
624 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
625 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
626 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
627 #define UART5_BASE (APB1PERIPH_BASE + 0x5000)
628 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
629 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
630 #define CAN_BASE (APB1PERIPH_BASE + 0x6400)
631 #define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
632 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
633 #define DAC_BASE (APB1PERIPH_BASE + 0x7400)
634 
635 #define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
636 #define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
637 #define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
638 #define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
639 #define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
640 #define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
641 #define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
642 #define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
643 #define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)
644 #define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
645 #define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
646 #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
647 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
648 #define TIM8_BASE (APB2PERIPH_BASE + 0x3400)
649 #define USART1_BASE (APB2PERIPH_BASE + 0x3800)
650 #define ADC3_BASE (APB2PERIPH_BASE + 0x3C00)
651 
652 #define SDIO_BASE (PERIPH_BASE + 0x18000)
653 
654 #define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
655 #define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
656 #define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
657 #define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
658 #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
659 #define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
660 #define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
661 #define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
662 #define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
663 #define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
664 #define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
665 #define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
666 #define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
667 #define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
668 #define RCC_BASE (AHBPERIPH_BASE + 0x1000)
669 #define CRC_BASE (AHBPERIPH_BASE + 0x3000)
670 
671 /* Flash registers base address */
672 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000)
673 /* Flash Option Bytes base address */
674 #define OB_BASE ((u32)0x1FFFF800)
675 
676 /* FSMC Bankx registers base address */
677 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
678 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
679 #define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)
680 #define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080)
681 #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
682 
683 /* Debug MCU registers base address */
684 #define DBGMCU_BASE ((u32)0xE0042000)
685 
686 /* System Control Space memory map */
687 #define SCS_BASE ((u32)0xE000E000)
688 
689 #define SysTick_BASE (SCS_BASE + 0x0010)
690 #define NVIC_BASE (SCS_BASE + 0x0100)
691 #define SCB_BASE (SCS_BASE + 0x0D00)
692 
693 /******************************************************************************/
694 /* Peripheral declaration */
695 /******************************************************************************/
696 
697 /*------------------------ Non Debug Mode ------------------------------------*/
698 #ifndef DEBUG
699 #ifdef _TIM2
700  #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
701 #endif /*_TIM2 */
702 
703 #ifdef _TIM3
704  #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
705 #endif /*_TIM3 */
706 
707 #ifdef _TIM4
708  #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
709 #endif /*_TIM4 */
710 
711 #ifdef _TIM5
712  #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
713 #endif /*_TIM5 */
714 
715 #ifdef _TIM6
716  #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
717 #endif /*_TIM6 */
718 
719 #ifdef _TIM7
720  #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
721 #endif /*_TIM7 */
722 
723 #ifdef _RTC
724  #define RTC ((RTC_TypeDef *) RTC_BASE)
725 #endif /*_RTC */
726 
727 #ifdef _WWDG
728  #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
729 #endif /*_WWDG */
730 
731 #ifdef _IWDG
732  #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
733 #endif /*_IWDG */
734 
735 #ifdef _SPI2
736  #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
737 #endif /*_SPI2 */
738 
739 #ifdef _SPI3
740  #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
741 #endif /*_SPI3 */
742 
743 #ifdef _USART2
744  #define USART2 ((USART_TypeDef *) USART2_BASE)
745 #endif /*_USART2 */
746 
747 #ifdef _USART3
748  #define USART3 ((USART_TypeDef *) USART3_BASE)
749 #endif /*_USART3 */
750 
751 #ifdef _UART4
752  #define UART4 ((USART_TypeDef *) UART4_BASE)
753 #endif /*_UART4 */
754 
755 #ifdef _UART5
756  #define UART5 ((USART_TypeDef *) UART5_BASE)
757 #endif /*_USART5 */
758 
759 #ifdef _I2C1
760  #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
761 #endif /*_I2C1 */
762 
763 #ifdef _I2C2
764  #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
765 #endif /*_I2C2 */
766 
767 #ifdef _CAN
768  #define CAN ((CAN_TypeDef *) CAN_BASE)
769 #endif /*_CAN */
770 
771 #ifdef _BKP
772  #define BKP ((BKP_TypeDef *) BKP_BASE)
773 #endif /*_BKP */
774 
775 #ifdef _PWR
776  #define PWR ((PWR_TypeDef *) PWR_BASE)
777 #endif /*_PWR */
778 
779 #ifdef _DAC
780  #define DAC ((DAC_TypeDef *) DAC_BASE)
781 #endif /*_DAC */
782 
783 #ifdef _AFIO
784  #define AFIO ((AFIO_TypeDef *) AFIO_BASE)
785 #endif /*_AFIO */
786 
787 #ifdef _EXTI
788  #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
789 #endif /*_EXTI */
790 
791 #ifdef _GPIOA
792  #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
793 #endif /*_GPIOA */
794 
795 #ifdef _GPIOB
796  #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
797 #endif /*_GPIOB */
798 
799 #ifdef _GPIOC
800  #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
801 #endif /*_GPIOC */
802 
803 #ifdef _GPIOD
804  #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
805 #endif /*_GPIOD */
806 
807 #ifdef _GPIOE
808  #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
809 #endif /*_GPIOE */
810 
811 #ifdef _GPIOF
812  #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
813 #endif /*_GPIOF */
814 
815 #ifdef _GPIOG
816  #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
817 #endif /*_GPIOG */
818 
819 #ifdef _ADC1
820  #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
821 #endif /*_ADC1 */
822 
823 #ifdef _ADC2
824  #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
825 #endif /*_ADC2 */
826 
827 #ifdef _TIM1
828  #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
829 #endif /*_TIM1 */
830 
831 #ifdef _SPI1
832  #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
833 #endif /*_SPI1 */
834 
835 #ifdef _TIM8
836  #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
837 #endif /*_TIM8 */
838 
839 #ifdef _USART1
840  #define USART1 ((USART_TypeDef *) USART1_BASE)
841 #endif /*_USART1 */
842 
843 #ifdef _ADC3
844  #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
845 #endif /*_ADC3 */
846 
847 #ifdef _SDIO
848  #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
849 #endif /*_SDIO */
850 
851 #ifdef _DMA
852  #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
853  #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
854 #endif /*_DMA */
855 
856 #ifdef _DMA1_Channel1
857  #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
858 #endif /*_DMA1_Channel1 */
859 
860 #ifdef _DMA1_Channel2
861  #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
862 #endif /*_DMA1_Channel2 */
863 
864 #ifdef _DMA1_Channel3
865  #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
866 #endif /*_DMA1_Channel3 */
867 
868 #ifdef _DMA1_Channel4
869  #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
870 #endif /*_DMA1_Channel4 */
871 
872 #ifdef _DMA1_Channel5
873  #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
874 #endif /*_DMA1_Channel5 */
875 
876 #ifdef _DMA1_Channel6
877  #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
878 #endif /*_DMA1_Channel6 */
879 
880 #ifdef _DMA1_Channel7
881  #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
882 #endif /*_DMA1_Channel7 */
883 
884 #ifdef _DMA2_Channel1
885  #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
886 #endif /*_DMA2_Channel1 */
887 
888 #ifdef _DMA2_Channel2
889  #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
890 #endif /*_DMA2_Channel2 */
891 
892 #ifdef _DMA2_Channel3
893  #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
894 #endif /*_DMA2_Channel3 */
895 
896 #ifdef _DMA2_Channel4
897  #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
898 #endif /*_DMA2_Channel4 */
899 
900 #ifdef _DMA2_Channel5
901  #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
902 #endif /*_DMA2_Channel5 */
903 
904 #ifdef _RCC
905  #define RCC ((RCC_TypeDef *) RCC_BASE)
906 #endif /*_RCC */
907 
908 #ifdef _CRC
909  #define CRC ((CRC_TypeDef *) CRC_BASE)
910 #endif /*_CRC */
911 
912 #ifdef _FLASH
913  #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
914  #define OB ((OB_TypeDef *) OB_BASE)
915 #endif /*_FLASH */
916 
917 #ifdef _FSMC
918  #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
919  #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
920  #define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
921  #define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
922  #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
923 #endif /*_FSMC */
924 
925 #ifdef _DBGMCU
926  #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
927 #endif /*_DBGMCU */
928 
929 #ifdef _SysTick
930  #define SysTick ((SysTick_TypeDef *) SysTick_BASE)
931 #endif /*_SysTick */
932 
933 #ifdef _NVIC
934  #define NVIC ((NVIC_TypeDef *) NVIC_BASE)
935  #define SCB ((SCB_TypeDef *) SCB_BASE)
936 #endif /*_NVIC */
937 
938 /*------------------------ Debug Mode ----------------------------------------*/
939 #else /* DEBUG */
940 #ifdef _TIM2
941  EXT TIM_TypeDef *TIM2;
942 #endif /*_TIM2 */
943 
944 #ifdef _TIM3
945  EXT TIM_TypeDef *TIM3;
946 #endif /*_TIM3 */
947 
948 #ifdef _TIM4
949  EXT TIM_TypeDef *TIM4;
950 #endif /*_TIM4 */
951 
952 #ifdef _TIM5
953  EXT TIM_TypeDef *TIM5;
954 #endif /*_TIM5 */
955 
956 #ifdef _TIM6
957  EXT TIM_TypeDef *TIM6;
958 #endif /*_TIM6 */
959 
960 #ifdef _TIM7
961  EXT TIM_TypeDef *TIM7;
962 #endif /*_TIM7 */
963 
964 #ifdef _RTC
965  EXT RTC_TypeDef *RTC;
966 #endif /*_RTC */
967 
968 #ifdef _WWDG
969  EXT WWDG_TypeDef *WWDG;
970 #endif /*_WWDG */
971 
972 #ifdef _IWDG
973  EXT IWDG_TypeDef *IWDG;
974 #endif /*_IWDG */
975 
976 #ifdef _SPI2
977  EXT SPI_TypeDef *SPI2;
978 #endif /*_SPI2 */
979 
980 #ifdef _SPI3
981  EXT SPI_TypeDef *SPI3;
982 #endif /*_SPI3 */
983 
984 #ifdef _USART2
985  EXT USART_TypeDef *USART2;
986 #endif /*_USART2 */
987 
988 #ifdef _USART3
989  EXT USART_TypeDef *USART3;
990 #endif /*_USART3 */
991 
992 #ifdef _UART4
993  EXT USART_TypeDef *UART4;
994 #endif /*_UART4 */
995 
996 #ifdef _UART5
997  EXT USART_TypeDef *UART5;
998 #endif /*_UART5 */
999 
1000 #ifdef _I2C1
1001  EXT I2C_TypeDef *I2C1;
1002 #endif /*_I2C1 */
1003 
1004 #ifdef _I2C2
1005  EXT I2C_TypeDef *I2C2;
1006 #endif /*_I2C2 */
1007 
1008 #ifdef _CAN
1009  EXT CAN_TypeDef *CAN;
1010 #endif /*_CAN */
1011 
1012 #ifdef _BKP
1013  EXT BKP_TypeDef *BKP;
1014 #endif /*_BKP */
1015 
1016 #ifdef _PWR
1017  EXT PWR_TypeDef *PWR;
1018 #endif /*_PWR */
1019 
1020 #ifdef _DAC
1021  EXT DAC_TypeDef *DAC;
1022 #endif /*_DAC */
1023 
1024 #ifdef _AFIO
1025  EXT AFIO_TypeDef *AFIO;
1026 #endif /*_AFIO */
1027 
1028 #ifdef _EXTI
1029  EXT EXTI_TypeDef *EXTI;
1030 #endif /*_EXTI */
1031 
1032 #ifdef _GPIOA
1033  EXT GPIO_TypeDef *GPIOA;
1034 #endif /*_GPIOA */
1035 
1036 #ifdef _GPIOB
1037  EXT GPIO_TypeDef *GPIOB;
1038 #endif /*_GPIOB */
1039 
1040 #ifdef _GPIOC
1041  EXT GPIO_TypeDef *GPIOC;
1042 #endif /*_GPIOC */
1043 
1044 #ifdef _GPIOD
1045  EXT GPIO_TypeDef *GPIOD;
1046 #endif /*_GPIOD */
1047 
1048 #ifdef _GPIOE
1049  EXT GPIO_TypeDef *GPIOE;
1050 #endif /*_GPIOE */
1051 
1052 #ifdef _GPIOF
1053  EXT GPIO_TypeDef *GPIOF;
1054 #endif /*_GPIOF */
1055 
1056 #ifdef _GPIOG
1057  EXT GPIO_TypeDef *GPIOG;
1058 #endif /*_GPIOG */
1059 
1060 #ifdef _ADC1
1061  EXT ADC_TypeDef *ADC1;
1062 #endif /*_ADC1 */
1063 
1064 #ifdef _ADC2
1065  EXT ADC_TypeDef *ADC2;
1066 #endif /*_ADC2 */
1067 
1068 #ifdef _TIM1
1069  EXT TIM_TypeDef *TIM1;
1070 #endif /*_TIM1 */
1071 
1072 #ifdef _SPI1
1073  EXT SPI_TypeDef *SPI1;
1074 #endif /*_SPI1 */
1075 
1076 #ifdef _TIM8
1077  EXT TIM_TypeDef *TIM8;
1078 #endif /*_TIM8 */
1079 
1080 #ifdef _USART1
1081  EXT USART_TypeDef *USART1;
1082 #endif /*_USART1 */
1083 
1084 #ifdef _ADC3
1085  EXT ADC_TypeDef *ADC3;
1086 #endif /*_ADC3 */
1087 
1088 #ifdef _SDIO
1089  EXT SDIO_TypeDef *SDIO;
1090 #endif /*_SDIO */
1091 
1092 #ifdef _DMA
1093  EXT DMA_TypeDef *DMA1;
1094  EXT DMA_TypeDef *DMA2;
1095 #endif /*_DMA */
1096 
1097 #ifdef _DMA1_Channel1
1098  EXT DMA_Channel_TypeDef *DMA1_Channel1;
1099 #endif /*_DMA1_Channel1 */
1100 
1101 #ifdef _DMA1_Channel2
1102  EXT DMA_Channel_TypeDef *DMA1_Channel2;
1103 #endif /*_DMA1_Channel2 */
1104 
1105 #ifdef _DMA1_Channel3
1106  EXT DMA_Channel_TypeDef *DMA1_Channel3;
1107 #endif /*_DMA1_Channel3 */
1108 
1109 #ifdef _DMA1_Channel4
1110  EXT DMA_Channel_TypeDef *DMA1_Channel4;
1111 #endif /*_DMA1_Channel4 */
1112 
1113 #ifdef _DMA1_Channel5
1114  EXT DMA_Channel_TypeDef *DMA1_Channel5;
1115 #endif /*_DMA1_Channel5 */
1116 
1117 #ifdef _DMA1_Channel6
1118  EXT DMA_Channel_TypeDef *DMA1_Channel6;
1119 #endif /*_DMA1_Channel6 */
1120 
1121 #ifdef _DMA1_Channel7
1122  EXT DMA_Channel_TypeDef *DMA1_Channel7;
1123 #endif /*_DMA1_Channel7 */
1124 
1125 #ifdef _DMA2_Channel1
1126  EXT DMA_Channel_TypeDef *DMA2_Channel1;
1127 #endif /*_DMA2_Channel1 */
1128 
1129 #ifdef _DMA2_Channel2
1130  EXT DMA_Channel_TypeDef *DMA2_Channel2;
1131 #endif /*_DMA2_Channel2 */
1132 
1133 #ifdef _DMA2_Channel3
1134  EXT DMA_Channel_TypeDef *DMA2_Channel3;
1135 #endif /*_DMA2_Channel3 */
1136 
1137 #ifdef _DMA2_Channel4
1138  EXT DMA_Channel_TypeDef *DMA2_Channel4;
1139 #endif /*_DMA2_Channel4 */
1140 
1141 #ifdef _DMA2_Channel5
1142  EXT DMA_Channel_TypeDef *DMA2_Channel5;
1143 #endif /*_DMA2_Channel5 */
1144 
1145 #ifdef _RCC
1146  EXT RCC_TypeDef *RCC;
1147 #endif /*_RCC */
1148 
1149 #ifdef _CRC
1150  EXT CRC_TypeDef *CRC;
1151 #endif /*_CRC */
1152 
1153 #ifdef _FLASH
1154  EXT FLASH_TypeDef *FLASH;
1155  EXT OB_TypeDef *OB;
1156 #endif /*_FLASH */
1157 
1158 #ifdef _FSMC
1159  EXT FSMC_Bank1_TypeDef *FSMC_Bank1;
1160  EXT FSMC_Bank1E_TypeDef *FSMC_Bank1E;
1161  EXT FSMC_Bank2_TypeDef *FSMC_Bank2;
1162  EXT FSMC_Bank3_TypeDef *FSMC_Bank3;
1163  EXT FSMC_Bank4_TypeDef *FSMC_Bank4;
1164 #endif /*_FSMC */
1165 
1166 #ifdef _DBGMCU
1167  EXT DBGMCU_TypeDef *DBGMCU;
1168 #endif /*_DBGMCU */
1169 
1170 #ifdef _SysTick
1171  EXT SysTick_TypeDef *SysTick;
1172 #endif /*_SysTick */
1173 
1174 #ifdef _NVIC
1175  EXT NVIC_TypeDef *NVIC;
1176  EXT SCB_TypeDef *SCB;
1177 #endif /*_NVIC */
1178 
1179 #endif /* DEBUG */
1180 
1181 /* Exported constants --------------------------------------------------------*/
1182 /******************************************************************************/
1183 /* */
1184 /* CRC calculation unit */
1185 /* */
1186 /******************************************************************************/
1187 
1188 /******************* Bit definition for CRC_DR register *********************/
1189 #define CRC_DR_DR ((u32)0xFFFFFFFF) /* Data register bits */
1190 
1191 
1192 /******************* Bit definition for CRC_IDR register ********************/
1193 #define CRC_IDR_IDR ((u8)0xFF) /* General-purpose 8-bit data register bits */
1194 
1195 
1196 /******************** Bit definition for CRC_CR register ********************/
1197 #define CRC_CR_RESET ((u8)0x01) /* RESET bit */
1198 
1199 
1200 
1201 /******************************************************************************/
1202 /* */
1203 /* Power Control */
1204 /* */
1205 /******************************************************************************/
1206 
1207 /******************** Bit definition for PWR_CR register ********************/
1208 #define PWR_CR_LPDS ((u16)0x0001) /* Low-Power Deepsleep */
1209 #define PWR_CR_PDDS ((u16)0x0002) /* Power Down Deepsleep */
1210 #define PWR_CR_CWUF ((u16)0x0004) /* Clear Wakeup Flag */
1211 #define PWR_CR_CSBF ((u16)0x0008) /* Clear Standby Flag */
1212 #define PWR_CR_PVDE ((u16)0x0010) /* Power Voltage Detector Enable */
1213 
1214 #define PWR_CR_PLS ((u16)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */
1215 #define PWR_CR_PLS_0 ((u16)0x0020) /* Bit 0 */
1216 #define PWR_CR_PLS_1 ((u16)0x0040) /* Bit 1 */
1217 #define PWR_CR_PLS_2 ((u16)0x0080) /* Bit 2 */
1218 
1219 /* PVD level configuration */
1220 #define PWR_CR_PLS_2V2 ((u16)0x0000) /* PVD level 2.2V */
1221 #define PWR_CR_PLS_2V3 ((u16)0x0020) /* PVD level 2.3V */
1222 #define PWR_CR_PLS_2V4 ((u16)0x0040) /* PVD level 2.4V */
1223 #define PWR_CR_PLS_2V5 ((u16)0x0060) /* PVD level 2.5V */
1224 #define PWR_CR_PLS_2V6 ((u16)0x0080) /* PVD level 2.6V */
1225 #define PWR_CR_PLS_2V7 ((u16)0x00A0) /* PVD level 2.7V */
1226 #define PWR_CR_PLS_2V8 ((u16)0x00C0) /* PVD level 2.8V */
1227 #define PWR_CR_PLS_2V9 ((u16)0x00E0) /* PVD level 2.9V */
1228 
1229 #define PWR_CR_DBP ((u16)0x0100) /* Disable Backup Domain write protection */
1230 
1231 
1232 /******************* Bit definition for PWR_CSR register ********************/
1233 #define PWR_CSR_WUF ((u16)0x0001) /* Wakeup Flag */
1234 #define PWR_CSR_SBF ((u16)0x0002) /* Standby Flag */
1235 #define PWR_CSR_PVDO ((u16)0x0004) /* PVD Output */
1236 #define PWR_CSR_EWUP ((u16)0x0100) /* Enable WKUP pin */
1237 
1238 
1239 
1240 /******************************************************************************/
1241 /* */
1242 /* Backup registers */
1243 /* */
1244 /******************************************************************************/
1245 
1246 /******************* Bit definition for BKP_DR1 register ********************/
1247 #define BKP_DR1_D ((u16)0xFFFF) /* Backup data */
1248 
1249 
1250 /******************* Bit definition for BKP_DR2 register ********************/
1251 #define BKP_DR2_D ((u16)0xFFFF) /* Backup data */
1252 
1253 
1254 /******************* Bit definition for BKP_DR3 register ********************/
1255 #define BKP_DR3_D ((u16)0xFFFF) /* Backup data */
1256 
1257 
1258 /******************* Bit definition for BKP_DR4 register ********************/
1259 #define BKP_DR4_D ((u16)0xFFFF) /* Backup data */
1260 
1261 
1262 /******************* Bit definition for BKP_DR5 register ********************/
1263 #define BKP_DR5_D ((u16)0xFFFF) /* Backup data */
1264 
1265 
1266 /******************* Bit definition for BKP_DR6 register ********************/
1267 #define BKP_DR6_D ((u16)0xFFFF) /* Backup data */
1268 
1269 
1270 /******************* Bit definition for BKP_DR7 register ********************/
1271 #define BKP_DR7_D ((u16)0xFFFF) /* Backup data */
1272 
1273 
1274 /******************* Bit definition for BKP_DR8 register ********************/
1275 #define BKP_DR8_D ((u16)0xFFFF) /* Backup data */
1276 
1277 
1278 /******************* Bit definition for BKP_DR9 register ********************/
1279 #define BKP_DR9_D ((u16)0xFFFF) /* Backup data */
1280 
1281 
1282 /******************* Bit definition for BKP_DR10 register *******************/
1283 #define BKP_DR10_D ((u16)0xFFFF) /* Backup data */
1284 
1285 
1286 /******************* Bit definition for BKP_DR11 register *******************/
1287 #define BKP_DR11_D ((u16)0xFFFF) /* Backup data */
1288 
1289 
1290 /******************* Bit definition for BKP_DR12 register *******************/
1291 #define BKP_DR12_D ((u16)0xFFFF) /* Backup data */
1292 
1293 
1294 /******************* Bit definition for BKP_DR13 register *******************/
1295 #define BKP_DR13_D ((u16)0xFFFF) /* Backup data */
1296 
1297 
1298 /******************* Bit definition for BKP_DR14 register *******************/
1299 #define BKP_DR14_D ((u16)0xFFFF) /* Backup data */
1300 
1301 
1302 /******************* Bit definition for BKP_DR15 register *******************/
1303 #define BKP_DR15_D ((u16)0xFFFF) /* Backup data */
1304 
1305 
1306 /******************* Bit definition for BKP_DR16 register *******************/
1307 #define BKP_DR16_D ((u16)0xFFFF) /* Backup data */
1308 
1309 
1310 /******************* Bit definition for BKP_DR17 register *******************/
1311 #define BKP_DR17_D ((u16)0xFFFF) /* Backup data */
1312 
1313 
1314 /****************** Bit definition for BKP_DR18 register ********************/
1315 #define BKP_DR18_D ((u16)0xFFFF) /* Backup data */
1316 
1317 
1318 /******************* Bit definition for BKP_DR19 register *******************/
1319 #define BKP_DR19_D ((u16)0xFFFF) /* Backup data */
1320 
1321 
1322 /******************* Bit definition for BKP_DR20 register *******************/
1323 #define BKP_DR20_D ((u16)0xFFFF) /* Backup data */
1324 
1325 
1326 /******************* Bit definition for BKP_DR21 register *******************/
1327 #define BKP_DR21_D ((u16)0xFFFF) /* Backup data */
1328 
1329 
1330 /******************* Bit definition for BKP_DR22 register *******************/
1331 #define BKP_DR22_D ((u16)0xFFFF) /* Backup data */
1332 
1333 
1334 /******************* Bit definition for BKP_DR23 register *******************/
1335 #define BKP_DR23_D ((u16)0xFFFF) /* Backup data */
1336 
1337 
1338 /******************* Bit definition for BKP_DR24 register *******************/
1339 #define BKP_DR24_D ((u16)0xFFFF) /* Backup data */
1340 
1341 
1342 /******************* Bit definition for BKP_DR25 register *******************/
1343 #define BKP_DR25_D ((u16)0xFFFF) /* Backup data */
1344 
1345 
1346 /******************* Bit definition for BKP_DR26 register *******************/
1347 #define BKP_DR26_D ((u16)0xFFFF) /* Backup data */
1348 
1349 
1350 /******************* Bit definition for BKP_DR27 register *******************/
1351 #define BKP_DR27_D ((u16)0xFFFF) /* Backup data */
1352 
1353 
1354 /******************* Bit definition for BKP_DR28 register *******************/
1355 #define BKP_DR28_D ((u16)0xFFFF) /* Backup data */
1356 
1357 
1358 /******************* Bit definition for BKP_DR29 register *******************/
1359 #define BKP_DR29_D ((u16)0xFFFF) /* Backup data */
1360 
1361 
1362 /******************* Bit definition for BKP_DR30 register *******************/
1363 #define BKP_DR30_D ((u16)0xFFFF) /* Backup data */
1364 
1365 
1366 /******************* Bit definition for BKP_DR31 register *******************/
1367 #define BKP_DR31_D ((u16)0xFFFF) /* Backup data */
1368 
1369 
1370 /******************* Bit definition for BKP_DR32 register *******************/
1371 #define BKP_DR32_D ((u16)0xFFFF) /* Backup data */
1372 
1373 
1374 /******************* Bit definition for BKP_DR33 register *******************/
1375 #define BKP_DR33_D ((u16)0xFFFF) /* Backup data */
1376 
1377 
1378 /******************* Bit definition for BKP_DR34 register *******************/
1379 #define BKP_DR34_D ((u16)0xFFFF) /* Backup data */
1380 
1381 
1382 /******************* Bit definition for BKP_DR35 register *******************/
1383 #define BKP_DR35_D ((u16)0xFFFF) /* Backup data */
1384 
1385 
1386 /******************* Bit definition for BKP_DR36 register *******************/
1387 #define BKP_DR36_D ((u16)0xFFFF) /* Backup data */
1388 
1389 
1390 /******************* Bit definition for BKP_DR37 register *******************/
1391 #define BKP_DR37_D ((u16)0xFFFF) /* Backup data */
1392 
1393 
1394 /******************* Bit definition for BKP_DR38 register *******************/
1395 #define BKP_DR38_D ((u16)0xFFFF) /* Backup data */
1396 
1397 
1398 /******************* Bit definition for BKP_DR39 register *******************/
1399 #define BKP_DR39_D ((u16)0xFFFF) /* Backup data */
1400 
1401 
1402 /******************* Bit definition for BKP_DR40 register *******************/
1403 #define BKP_DR40_D ((u16)0xFFFF) /* Backup data */
1404 
1405 
1406 /******************* Bit definition for BKP_DR41 register *******************/
1407 #define BKP_DR41_D ((u16)0xFFFF) /* Backup data */
1408 
1409 
1410 /******************* Bit definition for BKP_DR42 register *******************/
1411 #define BKP_DR42_D ((u16)0xFFFF) /* Backup data */
1412 
1413 
1414 /****************** Bit definition for BKP_RTCCR register *******************/
1415 #define BKP_RTCCR_CAL ((u16)0x007F) /* Calibration value */
1416 #define BKP_RTCCR_CCO ((u16)0x0080) /* Calibration Clock Output */
1417 #define BKP_RTCCR_ASOE ((u16)0x0100) /* Alarm or Second Output Enable */
1418 #define BKP_RTCCR_ASOS ((u16)0x0200) /* Alarm or Second Output Selection */
1419 
1420 
1421 /******************** Bit definition for BKP_CR register ********************/
1422 #define BKP_CR_TPE ((u8)0x01) /* TAMPER pin enable */
1423 #define BKP_CR_TPAL ((u8)0x02) /* TAMPER pin active level */
1424 
1425 
1426 /******************* Bit definition for BKP_CSR register ********************/
1427 #define BKP_CSR_CTE ((u16)0x0001) /* Clear Tamper event */
1428 #define BKP_CSR_CTI ((u16)0x0002) /* Clear Tamper Interrupt */
1429 #define BKP_CSR_TPIE ((u16)0x0004) /* TAMPER Pin interrupt enable */
1430 #define BKP_CSR_TEF ((u16)0x0100) /* Tamper Event Flag */
1431 #define BKP_CSR_TIF ((u16)0x0200) /* Tamper Interrupt Flag */
1432 
1433 
1434 
1435 /******************************************************************************/
1436 /* */
1437 /* Reset and Clock Control */
1438 /* */
1439 /******************************************************************************/
1440 
1441 
1442 /******************** Bit definition for RCC_CR register ********************/
1443 #define RCC_CR_HSION ((u32)0x00000001) /* Internal High Speed clock enable */
1444 #define RCC_CR_HSIRDY ((u32)0x00000002) /* Internal High Speed clock ready flag */
1445 #define RCC_CR_HSITRIM ((u32)0x000000F8) /* Internal High Speed clock trimming */
1446 #define RCC_CR_HSICAL ((u32)0x0000FF00) /* Internal High Speed clock Calibration */
1447 #define RCC_CR_HSEON ((u32)0x00010000) /* External High Speed clock enable */
1448 #define RCC_CR_HSERDY ((u32)0x00020000) /* External High Speed clock ready flag */
1449 #define RCC_CR_HSEBYP ((u32)0x00040000) /* External High Speed clock Bypass */
1450 #define RCC_CR_CSSON ((u32)0x00080000) /* Clock Security System enable */
1451 #define RCC_CR_PLLON ((u32)0x01000000) /* PLL enable */
1452 #define RCC_CR_PLLRDY ((u32)0x02000000) /* PLL clock ready flag */
1453 
1454 
1455 /******************* Bit definition for RCC_CFGR register *******************/
1456 #define RCC_CFGR_SW ((u32)0x00000003) /* SW[1:0] bits (System clock Switch) */
1457 #define RCC_CFGR_SW_0 ((u32)0x00000001) /* Bit 0 */
1458 #define RCC_CFGR_SW_1 ((u32)0x00000002) /* Bit 1 */
1459 
1460 /* SW configuration */
1461 #define RCC_CFGR_SW_HSI ((u32)0x00000000) /* HSI selected as system clock */
1462 #define RCC_CFGR_SW_HSE ((u32)0x00000001) /* HSE selected as system clock */
1463 #define RCC_CFGR_SW_PLL ((u32)0x00000002) /* PLL selected as system clock */
1464 
1465 #define RCC_CFGR_SWS ((u32)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */
1466 #define RCC_CFGR_SWS_0 ((u32)0x00000004) /* Bit 0 */
1467 #define RCC_CFGR_SWS_1 ((u32)0x00000008) /* Bit 1 */
1468 
1469 /* SWS configuration */
1470 #define RCC_CFGR_SWS_HSI ((u32)0x00000000) /* HSI oscillator used as system clock */
1471 #define RCC_CFGR_SWS_HSE ((u32)0x00000004) /* HSE oscillator used as system clock */
1472 #define RCC_CFGR_SWS_PLL ((u32)0x00000008) /* PLL used as system clock */
1473 
1474 #define RCC_CFGR_HPRE ((u32)0x000000F0) /* HPRE[3:0] bits (AHB prescaler) */
1475 #define RCC_CFGR_HPRE_0 ((u32)0x00000010) /* Bit 0 */
1476 #define RCC_CFGR_HPRE_1 ((u32)0x00000020) /* Bit 1 */
1477 #define RCC_CFGR_HPRE_2 ((u32)0x00000040) /* Bit 2 */
1478 #define RCC_CFGR_HPRE_3 ((u32)0x00000080) /* Bit 3 */
1479 
1480 /* HPRE configuration */
1481 #define RCC_CFGR_HPRE_DIV1 ((u32)0x00000000) /* SYSCLK not divided */
1482 #define RCC_CFGR_HPRE_DIV2 ((u32)0x00000080) /* SYSCLK divided by 2 */
1483 #define RCC_CFGR_HPRE_DIV4 ((u32)0x00000090) /* SYSCLK divided by 4 */
1484 #define RCC_CFGR_HPRE_DIV8 ((u32)0x000000A0) /* SYSCLK divided by 8 */
1485 #define RCC_CFGR_HPRE_DIV16 ((u32)0x000000B0) /* SYSCLK divided by 16 */
1486 #define RCC_CFGR_HPRE_DIV64 ((u32)0x000000C0) /* SYSCLK divided by 64 */
1487 #define RCC_CFGR_HPRE_DIV128 ((u32)0x000000D0) /* SYSCLK divided by 128 */
1488 #define RCC_CFGR_HPRE_DIV256 ((u32)0x000000E0) /* SYSCLK divided by 256 */
1489 #define RCC_CFGR_HPRE_DIV512 ((u32)0x000000F0) /* SYSCLK divided by 512 */
1490 
1491 #define RCC_CFGR_PPRE1 ((u32)0x00000700) /* PRE1[2:0] bits (APB1 prescaler) */
1492 #define RCC_CFGR_PPRE1_0 ((u32)0x00000100) /* Bit 0 */
1493 #define RCC_CFGR_PPRE1_1 ((u32)0x00000200) /* Bit 1 */
1494 #define RCC_CFGR_PPRE1_2 ((u32)0x00000400) /* Bit 2 */
1495 
1496 /* PPRE1 configuration */
1497 #define RCC_CFGR_PPRE1_DIV1 ((u32)0x00000000) /* HCLK not divided */
1498 #define RCC_CFGR_PPRE1_DIV2 ((u32)0x00000400) /* HCLK divided by 2 */
1499 #define RCC_CFGR_PPRE1_DIV4 ((u32)0x00000500) /* HCLK divided by 4 */
1500 #define RCC_CFGR_PPRE1_DIV8 ((u32)0x00000600) /* HCLK divided by 8 */
1501 #define RCC_CFGR_PPRE1_DIV16 ((u32)0x00000700) /* HCLK divided by 16 */
1502 
1503 #define RCC_CFGR_PPRE2 ((u32)0x00003800) /* PRE2[2:0] bits (APB2 prescaler) */
1504 #define RCC_CFGR_PPRE2_0 ((u32)0x00000800) /* Bit 0 */
1505 #define RCC_CFGR_PPRE2_1 ((u32)0x00001000) /* Bit 1 */
1506 #define RCC_CFGR_PPRE2_2 ((u32)0x00002000) /* Bit 2 */
1507 
1508 /* PPRE2 configuration */
1509 #define RCC_CFGR_PPRE2_DIV1 ((u32)0x00000000) /* HCLK not divided */
1510 #define RCC_CFGR_PPRE2_DIV2 ((u32)0x00002000) /* HCLK divided by 2 */
1511 #define RCC_CFGR_PPRE2_DIV4 ((u32)0x00002800) /* HCLK divided by 4 */
1512 #define RCC_CFGR_PPRE2_DIV8 ((u32)0x00003000) /* HCLK divided by 8 */
1513 #define RCC_CFGR_PPRE2_DIV16 ((u32)0x00003800) /* HCLK divided by 16 */
1514 
1515 #define RCC_CFGR_ADCPRE ((u32)0x0000C000) /* ADCPRE[1:0] bits (ADC prescaler) */
1516 #define RCC_CFGR_ADCPRE_0 ((u32)0x00004000) /* Bit 0 */
1517 #define RCC_CFGR_ADCPRE_1 ((u32)0x00008000) /* Bit 1 */
1518 
1519 /* ADCPPRE configuration */
1520 #define RCC_CFGR_ADCPRE_DIV2 ((u32)0x00000000) /* PCLK2 divided by 2 */
1521 #define RCC_CFGR_ADCPRE_DIV4 ((u32)0x00004000) /* PCLK2 divided by 4 */
1522 #define RCC_CFGR_ADCPRE_DIV6 ((u32)0x00008000) /* PCLK2 divided by 6 */
1523 #define RCC_CFGR_ADCPRE_DIV8 ((u32)0x0000C000) /* PCLK2 divided by 8 */
1524 
1525 #define RCC_CFGR_PLLSRC ((u32)0x00010000) /* PLL entry clock source */
1526 #define RCC_CFGR_PLLXTPRE ((u32)0x00020000) /* HSE divider for PLL entry */
1527 
1528 #define RCC_CFGR_PLLMULL ((u32)0x003C0000) /* PLLMUL[3:0] bits (PLL multiplication factor) */
1529 #define RCC_CFGR_PLLMULL_0 ((u32)0x00040000) /* Bit 0 */
1530 #define RCC_CFGR_PLLMULL_1 ((u32)0x00080000) /* Bit 1 */
1531 #define RCC_CFGR_PLLMULL_2 ((u32)0x00100000) /* Bit 2 */
1532 #define RCC_CFGR_PLLMULL_3 ((u32)0x00200000) /* Bit 3 */
1533 
1534 /* PLLMUL configuration */
1535 #define RCC_CFGR_PLLMULL2 ((u32)0x00000000) /* PLL input clock*2 */
1536 #define RCC_CFGR_PLLMULL3 ((u32)0x00040000) /* PLL input clock*3 */
1537 #define RCC_CFGR_PLLMULL4 ((u32)0x00080000) /* PLL input clock*4 */
1538 #define RCC_CFGR_PLLMULL5 ((u32)0x000C0000) /* PLL input clock*5 */
1539 #define RCC_CFGR_PLLMULL6 ((u32)0x00100000) /* PLL input clock*6 */
1540 #define RCC_CFGR_PLLMULL7 ((u32)0x00140000) /* PLL input clock*7 */
1541 #define RCC_CFGR_PLLMULL8 ((u32)0x00180000) /* PLL input clock*8 */
1542 #define RCC_CFGR_PLLMULL9 ((u32)0x001C0000) /* PLL input clock*9 */
1543 #define RCC_CFGR_PLLMULL10 ((u32)0x00200000) /* PLL input clock10 */
1544 #define RCC_CFGR_PLLMULL11 ((u32)0x00240000) /* PLL input clock*11 */
1545 #define RCC_CFGR_PLLMULL12 ((u32)0x00280000) /* PLL input clock*12 */
1546 #define RCC_CFGR_PLLMULL13 ((u32)0x002C0000) /* PLL input clock*13 */
1547 #define RCC_CFGR_PLLMULL14 ((u32)0x00300000) /* PLL input clock*14 */
1548 #define RCC_CFGR_PLLMULL15 ((u32)0x00340000) /* PLL input clock*15 */
1549 #define RCC_CFGR_PLLMULL16 ((u32)0x00380000) /* PLL input clock*16 */
1550 
1551 #define RCC_CFGR_USBPRE ((u32)0x00400000) /* USB prescaler */
1552 
1553 #define RCC_CFGR_MCO ((u32)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */
1554 #define RCC_CFGR_MCO_0 ((u32)0x01000000) /* Bit 0 */
1555 #define RCC_CFGR_MCO_1 ((u32)0x02000000) /* Bit 1 */
1556 #define RCC_CFGR_MCO_2 ((u32)0x04000000) /* Bit 2 */
1557 
1558 /* MCO configuration */
1559 #define RCC_CFGR_MCO_NOCLOCK ((u32)0x00000000) /* No clock */
1560 #define RCC_CFGR_MCO_SYSCLK ((u32)0x04000000) /* System clock selected */
1561 #define RCC_CFGR_MCO_HSI ((u32)0x05000000) /* Internal 8 MHz RC oscillator clock selected */
1562 #define RCC_CFGR_MCO_HSE ((u32)0x06000000) /* External 1-25 MHz oscillator clock selected */
1563 #define RCC_CFGR_MCO_PLL ((u32)0x07000000) /* PLL clock divided by 2 selected*/
1564 
1565 
1566 /******************* Bit definition for RCC_CIR register ********************/
1567 #define RCC_CIR_LSIRDYF ((u32)0x00000001) /* LSI Ready Interrupt flag */
1568 #define RCC_CIR_LSERDYF ((u32)0x00000002) /* LSE Ready Interrupt flag */
1569 #define RCC_CIR_HSIRDYF ((u32)0x00000004) /* HSI Ready Interrupt flag */
1570 #define RCC_CIR_HSERDYF ((u32)0x00000008) /* HSE Ready Interrupt flag */
1571 #define RCC_CIR_PLLRDYF ((u32)0x00000010) /* PLL Ready Interrupt flag */
1572 #define RCC_CIR_CSSF ((u32)0x00000080) /* Clock Security System Interrupt flag */
1573 #define RCC_CIR_LSIRDYIE ((u32)0x00000100) /* LSI Ready Interrupt Enable */
1574 #define RCC_CIR_LSERDYIE ((u32)0x00000200) /* LSE Ready Interrupt Enable */
1575 #define RCC_CIR_HSIRDYIE ((u32)0x00000400) /* HSI Ready Interrupt Enable */
1576 #define RCC_CIR_HSERDYIE ((u32)0x00000800) /* HSE Ready Interrupt Enable */
1577 #define RCC_CIR_PLLRDYIE ((u32)0x00001000) /* PLL Ready Interrupt Enable */
1578 #define RCC_CIR_LSIRDYC ((u32)0x00010000) /* LSI Ready Interrupt Clear */
1579 #define RCC_CIR_LSERDYC ((u32)0x00020000) /* LSE Ready Interrupt Clear */
1580 #define RCC_CIR_HSIRDYC ((u32)0x00040000) /* HSI Ready Interrupt Clear */
1581 #define RCC_CIR_HSERDYC ((u32)0x00080000) /* HSE Ready Interrupt Clear */
1582 #define RCC_CIR_PLLRDYC ((u32)0x00100000) /* PLL Ready Interrupt Clear */
1583 #define RCC_CIR_CSSC ((u32)0x00800000) /* Clock Security System Interrupt Clear */
1584 
1585 
1586 /***************** Bit definition for RCC_APB2RSTR register *****************/
1587 #define RCC_APB2RSTR_AFIORST ((u16)0x0001) /* Alternate Function I/O reset */
1588 #define RCC_APB2RSTR_IOPARST ((u16)0x0004) /* I/O port A reset */
1589 #define RCC_APB2RSTR_IOPBRST ((u16)0x0008) /* IO port B reset */
1590 #define RCC_APB2RSTR_IOPCRST ((u16)0x0010) /* IO port C reset */
1591 #define RCC_APB2RSTR_IOPDRST ((u16)0x0020) /* IO port D reset */
1592 #define RCC_APB2RSTR_IOPERST ((u16)0x0040) /* IO port E reset */
1593 #define RCC_APB2RSTR_IOPFRST ((u16)0x0080) /* IO port F reset */
1594 #define RCC_APB2RSTR_IOPGRST ((u16)0x0100) /* IO port G reset */
1595 #define RCC_APB2RSTR_ADC1RST ((u16)0x0200) /* ADC 1 interface reset */
1596 #define RCC_APB2RSTR_ADC2RST ((u16)0x0400) /* ADC 2 interface reset */
1597 #define RCC_APB2RSTR_TIM1RST ((u16)0x0800) /* TIM1 Timer reset */
1598 #define RCC_APB2RSTR_SPI1RST ((u16)0x1000) /* SPI 1 reset */
1599 #define RCC_APB2RSTR_TIM8RST ((u16)0x2000) /* TIM8 Timer reset */
1600 #define RCC_APB2RSTR_USART1RST ((u16)0x4000) /* USART1 reset */
1601 #define RCC_APB2RSTR_ADC3RST ((u16)0x8000) /* ADC3 interface reset */
1602 
1603 
1604 /***************** Bit definition for RCC_APB1RSTR register *****************/
1605 #define RCC_APB1RSTR_TIM2RST ((u32)0x00000001) /* Timer 2 reset */
1606 #define RCC_APB1RSTR_TIM3RST ((u32)0x00000002) /* Timer 3 reset */
1607 #define RCC_APB1RSTR_TIM4RST ((u32)0x00000004) /* Timer 4 reset */
1608 #define RCC_APB1RSTR_TIM5RST ((u32)0x00000008) /* Timer 5 reset */
1609 #define RCC_APB1RSTR_TIM6RST ((u32)0x00000010) /* Timer 6 reset */
1610 #define RCC_APB1RSTR_TIM7RST ((u32)0x00000020) /* Timer 7 reset */
1611 #define RCC_APB1RSTR_WWDGRST ((u32)0x00000800) /* Window Watchdog reset */
1612 #define RCC_APB1RSTR_SPI2RST ((u32)0x00004000) /* SPI 2 reset */
1613 #define RCC_APB1RSTR_SPI3RST ((u32)0x00008000) /* SPI 3 reset */
1614 #define RCC_APB1RSTR_USART2RST ((u32)0x00020000) /* USART 2 reset */
1615 #define RCC_APB1RSTR_USART3RST ((u32)0x00040000) /* RUSART 3 reset */
1616 #define RCC_APB1RSTR_UART4RST ((u32)0x00080000) /* USART 4 reset */
1617 #define RCC_APB1RSTR_UART5RST ((u32)0x00100000) /* USART 5 reset */
1618 #define RCC_APB1RSTR_I2C1RST ((u32)0x00200000) /* I2C 1 reset */
1619 #define RCC_APB1RSTR_I2C2RST ((u32)0x00400000) /* I2C 2 reset */
1620 #define RCC_APB1RSTR_USBRST ((u32)0x00800000) /* USB reset */
1621 #define RCC_APB1RSTR_CANRST ((u32)0x02000000) /* CAN reset */
1622 #define RCC_APB1RSTR_BKPRST ((u32)0x08000000) /* Backup interface reset */
1623 #define RCC_APB1RSTR_PWRRST ((u32)0x10000000) /* Power interface reset */
1624 #define RCC_APB1RSTR_DACRST ((u32)0x20000000) /* DAC interface reset */
1625 
1626 
1627 /****************** Bit definition for RCC_AHBENR register ******************/
1628 #define RCC_AHBENR_DMA1EN ((u16)0x0001) /* DMA1 clock enable */
1629 #define RCC_AHBENR_DMA2EN ((u16)0x0002) /* DMA2 clock enable */
1630 #define RCC_AHBENR_SRAMEN ((u16)0x0004) /* SRAM interface clock enable */
1631 #define RCC_AHBENR_FLITFEN ((u16)0x0010) /* FLITF clock enable */
1632 #define RCC_AHBENR_CRCEN ((u16)0x0040) /* CRC clock enable */
1633 #define RCC_AHBENR_FSMCEN ((u16)0x0100) /* FSMC clock enable */
1634 #define RCC_AHBENR_SDIOEN ((u16)0x0400) /* SDIO clock enable */
1635 
1636 
1637 /****************** Bit definition for RCC_APB2ENR register *****************/
1638 #define RCC_APB2ENR_AFIOEN ((u16)0x0001) /* Alternate Function I/O clock enable */
1639 #define RCC_APB2ENR_IOPAEN ((u16)0x0004) /* I/O port A clock enable */
1640 #define RCC_APB2ENR_IOPBEN ((u16)0x0008) /* I/O port B clock enable */
1641 #define RCC_APB2ENR_IOPCEN ((u16)0x0010) /* I/O port C clock enable */
1642 #define RCC_APB2ENR_IOPDEN ((u16)0x0020) /* I/O port D clock enable */
1643 #define RCC_APB2ENR_IOPEEN ((u16)0x0040) /* I/O port E clock enable */
1644 #define RCC_APB2ENR_IOPFEN ((u16)0x0080) /* I/O port F clock enable */
1645 #define RCC_APB2ENR_IOPGEN ((u16)0x0100) /* I/O port G clock enable */
1646 #define RCC_APB2ENR_ADC1EN ((u16)0x0200) /* ADC 1 interface clock enable */
1647 #define RCC_APB2ENR_ADC2EN ((u16)0x0400) /* ADC 2 interface clock enable */
1648 #define RCC_APB2ENR_TIM1EN ((u16)0x0800) /* TIM1 Timer clock enable */
1649 #define RCC_APB2ENR_SPI1EN ((u16)0x1000) /* SPI 1 clock enable */
1650 #define RCC_APB2ENR_TIM8EN ((u16)0x2000) /* TIM8 Timer clock enable */
1651 #define RCC_APB2ENR_USART1EN ((u16)0x4000) /* USART1 clock enable */
1652 #define RCC_APB2ENR_ADC3EN ((u16)0x8000) /* DMA1 clock enable */
1653 
1654 
1655 /***************** Bit definition for RCC_APB1ENR register ******************/
1656 #define RCC_APB1ENR_TIM2EN ((u32)0x00000001) /* Timer 2 clock enabled*/
1657 #define RCC_APB1ENR_TIM3EN ((u32)0x00000002) /* Timer 3 clock enable */
1658 #define RCC_APB1ENR_TIM4EN ((u32)0x00000004) /* Timer 4 clock enable */
1659 #define RCC_APB1ENR_TIM5EN ((u32)0x00000008) /* Timer 5 clock enable */
1660 #define RCC_APB1ENR_TIM6EN ((u32)0x00000010) /* Timer 6 clock enable */
1661 #define RCC_APB1ENR_TIM7EN ((u32)0x00000020) /* Timer 7 clock enable */
1662 #define RCC_APB1ENR_WWDGEN ((u32)0x00000800) /* Window Watchdog clock enable */
1663 #define RCC_APB1ENR_SPI2EN ((u32)0x00004000) /* SPI 2 clock enable */
1664 #define RCC_APB1ENR_SPI3EN ((u32)0x00008000) /* SPI 3 clock enable */
1665 #define RCC_APB1ENR_USART2EN ((u32)0x00020000) /* USART 2 clock enable */
1666 #define RCC_APB1ENR_USART3EN ((u32)0x00040000) /* USART 3 clock enable */
1667 #define RCC_APB1ENR_UART4EN ((u32)0x00080000) /* USART 4 clock enable */
1668 #define RCC_APB1ENR_UART5EN ((u32)0x00100000) /* USART 5 clock enable */
1669 #define RCC_APB1ENR_I2C1EN ((u32)0x00200000) /* I2C 1 clock enable */
1670 #define RCC_APB1ENR_I2C2EN ((u32)0x00400000) /* I2C 2 clock enable */
1671 #define RCC_APB1ENR_USBEN ((u32)0x00800000) /* USB clock enable */
1672 #define RCC_APB1ENR_CANEN ((u32)0x02000000) /* CAN clock enable */
1673 #define RCC_APB1ENR_BKPEN ((u32)0x08000000) /* Backup interface clock enable */
1674 #define RCC_APB1ENR_PWREN ((u32)0x10000000) /* Power interface clock enable */
1675 #define RCC_APB1ENR_DACEN ((u32)0x20000000) /* DAC interface clock enable */
1676 
1677 
1678 /******************* Bit definition for RCC_BDCR register *******************/
1679 #define RCC_BDCR_LSEON ((u32)0x00000001) /* External Low Speed oscillator enable */
1680 #define RCC_BDCR_LSERDY ((u32)0x00000002) /* External Low Speed oscillator Ready */
1681 #define RCC_BDCR_LSEBYP ((u32)0x00000004) /* External Low Speed oscillator Bypass */
1682 
1683 #define RCC_BDCR_RTCSEL ((u32)0x00000300) /* RTCSEL[1:0] bits (RTC clock source selection) */
1684 #define RCC_BDCR_RTCSEL_0 ((u32)0x00000100) /* Bit 0 */
1685 #define RCC_BDCR_RTCSEL_1 ((u32)0x00000200) /* Bit 1 */
1686 /* RTC congiguration */
1687 #define RCC_BDCR_RTCSEL_NOCLOCK ((u32)0x00000000) /* No clock */
1688 #define RCC_BDCR_RTCSEL_LSE ((u32)0x00000100) /* LSE oscillator clock used as RTC clock */
1689 #define RCC_BDCR_RTCSEL_LSI ((u32)0x00000200) /* LSI oscillator clock used as RTC clock */
1690 #define RCC_BDCR_RTCSEL_HSE ((u32)0x00000300) /* HSE oscillator clock divided by 128 used as RTC clock */
1691 
1692 #define RCC_BDCR_RTCEN ((u32)0x00008000) /* RTC clock enable */
1693 #define RCC_BDCR_BDRST ((u32)0x00010000) /* Backup domain software reset */
1694 
1695 
1696 /******************* Bit definition for RCC_CSR register ********************/
1697 #define RCC_CSR_LSION ((u32)0x00000001) /* Internal Low Speed oscillator enable */
1698 #define RCC_CSR_LSIRDY ((u32)0x00000002) /* Internal Low Speed oscillator Ready */
1699 #define RCC_CSR_RMVF ((u32)0x01000000) /* Remove reset flag */
1700 #define RCC_CSR_PINRSTF ((u32)0x04000000) /* PIN reset flag */
1701 #define RCC_CSR_PORRSTF ((u32)0x08000000) /* POR/PDR reset flag */
1702 #define RCC_CSR_SFTRSTF ((u32)0x10000000) /* Software Reset flag */
1703 #define RCC_CSR_IWDGRSTF ((u32)0x20000000) /* Independent Watchdog reset flag */
1704 #define RCC_CSR_WWDGRSTF ((u32)0x40000000) /* Window watchdog reset flag */
1705 #define RCC_CSR_LPWRRSTF ((u32)0x80000000) /* Low-Power reset flag */
1706 
1707 
1708 
1709 /******************************************************************************/
1710 /* */
1711 /* General Purpose and Alternate Function IO */
1712 /* */
1713 /******************************************************************************/
1714 
1715 /******************* Bit definition for GPIO_CRL register *******************/
1716 #define GPIO_CRL_MODE ((u32)0x33333333) /* Port x mode bits */
1717 
1718 #define GPIO_CRL_MODE0 ((u32)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */
1719 #define GPIO_CRL_MODE0_0 ((u32)0x00000001) /* Bit 0 */
1720 #define GPIO_CRL_MODE0_1 ((u32)0x00000002) /* Bit 1 */
1721 
1722 #define GPIO_CRL_MODE1 ((u32)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */
1723 #define GPIO_CRL_MODE1_0 ((u32)0x00000010) /* Bit 0 */
1724 #define GPIO_CRL_MODE1_1 ((u32)0x00000020) /* Bit 1 */
1725 
1726 #define GPIO_CRL_MODE2 ((u32)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */
1727 #define GPIO_CRL_MODE2_0 ((u32)0x00000100) /* Bit 0 */
1728 #define GPIO_CRL_MODE2_1 ((u32)0x00000200) /* Bit 1 */
1729 
1730 #define GPIO_CRL_MODE3 ((u32)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */
1731 #define GPIO_CRL_MODE3_0 ((u32)0x00001000) /* Bit 0 */
1732 #define GPIO_CRL_MODE3_1 ((u32)0x00002000) /* Bit 1 */
1733 
1734 #define GPIO_CRL_MODE4 ((u32)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */
1735 #define GPIO_CRL_MODE4_0 ((u32)0x00010000) /* Bit 0 */
1736 #define GPIO_CRL_MODE4_1 ((u32)0x00020000) /* Bit 1 */
1737 
1738 #define GPIO_CRL_MODE5 ((u32)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */
1739 #define GPIO_CRL_MODE5_0 ((u32)0x00100000) /* Bit 0 */
1740 #define GPIO_CRL_MODE5_1 ((u32)0x00200000) /* Bit 1 */
1741 
1742 #define GPIO_CRL_MODE6 ((u32)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */
1743 #define GPIO_CRL_MODE6_0 ((u32)0x01000000) /* Bit 0 */
1744 #define GPIO_CRL_MODE6_1 ((u32)0x02000000) /* Bit 1 */
1745 
1746 #define GPIO_CRL_MODE7 ((u32)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */
1747 #define GPIO_CRL_MODE7_0 ((u32)0x10000000) /* Bit 0 */
1748 #define GPIO_CRL_MODE7_1 ((u32)0x20000000) /* Bit 1 */
1749 
1750 
1751 #define GPIO_CRL_CNF ((u32)0xCCCCCCCC) /* Port x configuration bits */
1752 
1753 #define GPIO_CRL_CNF0 ((u32)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */
1754 #define GPIO_CRL_CNF0_0 ((u32)0x00000004) /* Bit 0 */
1755 #define GPIO_CRL_CNF0_1 ((u32)0x00000008) /* Bit 1 */
1756 
1757 #define GPIO_CRL_CNF1 ((u32)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */
1758 #define GPIO_CRL_CNF1_0 ((u32)0x00000040) /* Bit 0 */
1759 #define GPIO_CRL_CNF1_1 ((u32)0x00000080) /* Bit 1 */
1760 
1761 #define GPIO_CRL_CNF2 ((u32)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */
1762 #define GPIO_CRL_CNF2_0 ((u32)0x00000400) /* Bit 0 */
1763 #define GPIO_CRL_CNF2_1 ((u32)0x00000800) /* Bit 1 */
1764 
1765 #define GPIO_CRL_CNF3 ((u32)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */
1766 #define GPIO_CRL_CNF3_0 ((u32)0x00004000) /* Bit 0 */
1767 #define GPIO_CRL_CNF3_1 ((u32)0x00008000) /* Bit 1 */
1768 
1769 #define GPIO_CRL_CNF4 ((u32)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */
1770 #define GPIO_CRL_CNF4_0 ((u32)0x00040000) /* Bit 0 */
1771 #define GPIO_CRL_CNF4_1 ((u32)0x00080000) /* Bit 1 */
1772 
1773 #define GPIO_CRL_CNF5 ((u32)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */
1774 #define GPIO_CRL_CNF5_0 ((u32)0x00400000) /* Bit 0 */
1775 #define GPIO_CRL_CNF5_1 ((u32)0x00800000) /* Bit 1 */
1776 
1777 #define GPIO_CRL_CNF6 ((u32)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */
1778 #define GPIO_CRL_CNF6_0 ((u32)0x04000000) /* Bit 0 */
1779 #define GPIO_CRL_CNF6_1 ((u32)0x08000000) /* Bit 1 */
1780 
1781 #define GPIO_CRL_CNF7 ((u32)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */
1782 #define GPIO_CRL_CNF7_0 ((u32)0x40000000) /* Bit 0 */
1783 #define GPIO_CRL_CNF7_1 ((u32)0x80000000) /* Bit 1 */
1784 
1785 
1786 /******************* Bit definition for GPIO_CRH register *******************/
1787 #define GPIO_CRH_MODE ((u32)0x33333333) /* Port x mode bits */
1788 
1789 #define GPIO_CRH_MODE8 ((u32)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */
1790 #define GPIO_CRH_MODE8_0 ((u32)0x00000001) /* Bit 0 */
1791 #define GPIO_CRH_MODE8_1 ((u32)0x00000002) /* Bit 1 */
1792 
1793 #define GPIO_CRH_MODE9 ((u32)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */
1794 #define GPIO_CRH_MODE9_0 ((u32)0x00000010) /* Bit 0 */
1795 #define GPIO_CRH_MODE9_1 ((u32)0x00000020) /* Bit 1 */
1796 
1797 #define GPIO_CRH_MODE10 ((u32)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */
1798 #define GPIO_CRH_MODE10_0 ((u32)0x00000100) /* Bit 0 */
1799 #define GPIO_CRH_MODE10_1 ((u32)0x00000200) /* Bit 1 */
1800 
1801 #define GPIO_CRH_MODE11 ((u32)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */
1802 #define GPIO_CRH_MODE11_0 ((u32)0x00001000) /* Bit 0 */
1803 #define GPIO_CRH_MODE11_1 ((u32)0x00002000) /* Bit 1 */
1804 
1805 #define GPIO_CRH_MODE12 ((u32)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */
1806 #define GPIO_CRH_MODE12_0 ((u32)0x00010000) /* Bit 0 */
1807 #define GPIO_CRH_MODE12_1 ((u32)0x00020000) /* Bit 1 */
1808 
1809 #define GPIO_CRH_MODE13 ((u32)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */
1810 #define GPIO_CRH_MODE13_0 ((u32)0x00100000) /* Bit 0 */
1811 #define GPIO_CRH_MODE13_1 ((u32)0x00200000) /* Bit 1 */
1812 
1813 #define GPIO_CRH_MODE14 ((u32)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */
1814 #define GPIO_CRH_MODE14_0 ((u32)0x01000000) /* Bit 0 */
1815 #define GPIO_CRH_MODE14_1 ((u32)0x02000000) /* Bit 1 */
1816 
1817 #define GPIO_CRH_MODE15 ((u32)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */
1818 #define GPIO_CRH_MODE15_0 ((u32)0x10000000) /* Bit 0 */
1819 #define GPIO_CRH_MODE15_1 ((u32)0x20000000) /* Bit 1 */
1820 
1821 
1822 #define GPIO_CRH_CNF ((u32)0xCCCCCCCC) /* Port x configuration bits */
1823 
1824 #define GPIO_CRH_CNF8 ((u32)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */
1825 #define GPIO_CRH_CNF8_0 ((u32)0x00000004) /* Bit 0 */
1826 #define GPIO_CRH_CNF8_1 ((u32)0x00000008) /* Bit 1 */
1827 
1828 #define GPIO_CRH_CNF9 ((u32)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */
1829 #define GPIO_CRH_CNF9_0 ((u32)0x00000040) /* Bit 0 */
1830 #define GPIO_CRH_CNF9_1 ((u32)0x00000080) /* Bit 1 */
1831 
1832 #define GPIO_CRH_CNF10 ((u32)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */
1833 #define GPIO_CRH_CNF10_0 ((u32)0x00000400) /* Bit 0 */
1834 #define GPIO_CRH_CNF10_1 ((u32)0x00000800) /* Bit 1 */
1835 
1836 #define GPIO_CRH_CNF11 ((u32)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */
1837 #define GPIO_CRH_CNF11_0 ((u32)0x00004000) /* Bit 0 */
1838 #define GPIO_CRH_CNF11_1 ((u32)0x00008000) /* Bit 1 */
1839 
1840 #define GPIO_CRH_CNF12 ((u32)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */
1841 #define GPIO_CRH_CNF12_0 ((u32)0x00040000) /* Bit 0 */
1842 #define GPIO_CRH_CNF12_1 ((u32)0x00080000) /* Bit 1 */
1843 
1844 #define GPIO_CRH_CNF13 ((u32)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */
1845 #define GPIO_CRH_CNF13_0 ((u32)0x00400000) /* Bit 0 */
1846 #define GPIO_CRH_CNF13_1 ((u32)0x00800000) /* Bit 1 */
1847 
1848 #define GPIO_CRH_CNF14 ((u32)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */
1849 #define GPIO_CRH_CNF14_0 ((u32)0x04000000) /* Bit 0 */
1850 #define GPIO_CRH_CNF14_1 ((u32)0x08000000) /* Bit 1 */
1851 
1852 #define GPIO_CRH_CNF15 ((u32)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */
1853 #define GPIO_CRH_CNF15_0 ((u32)0x40000000) /* Bit 0 */
1854 #define GPIO_CRH_CNF15_1 ((u32)0x80000000) /* Bit 1 */
1855 
1856 
1857 /******************* Bit definition for GPIO_IDR register *******************/
1858 #define GPIO_IDR_IDR0 ((u16)0x0001) /* Port input data, bit 0 */
1859 #define GPIO_IDR_IDR1 ((u16)0x0002) /* Port input data, bit 1 */
1860 #define GPIO_IDR_IDR2 ((u16)0x0004) /* Port input data, bit 2 */
1861 #define GPIO_IDR_IDR3 ((u16)0x0008) /* Port input data, bit 3 */
1862 #define GPIO_IDR_IDR4 ((u16)0x0010) /* Port input data, bit 4 */
1863 #define GPIO_IDR_IDR5 ((u16)0x0020) /* Port input data, bit 5 */
1864 #define GPIO_IDR_IDR6 ((u16)0x0040) /* Port input data, bit 6 */
1865 #define GPIO_IDR_IDR7 ((u16)0x0080) /* Port input data, bit 7 */
1866 #define GPIO_IDR_IDR8 ((u16)0x0100) /* Port input data, bit 8 */
1867 #define GPIO_IDR_IDR9 ((u16)0x0200) /* Port input data, bit 9 */
1868 #define GPIO_IDR_IDR10 ((u16)0x0400) /* Port input data, bit 10 */
1869 #define GPIO_IDR_IDR11 ((u16)0x0800) /* Port input data, bit 11 */
1870 #define GPIO_IDR_IDR12 ((u16)0x1000) /* Port input data, bit 12 */
1871 #define GPIO_IDR_IDR13 ((u16)0x2000) /* Port input data, bit 13 */
1872 #define GPIO_IDR_IDR14 ((u16)0x4000) /* Port input data, bit 14 */
1873 #define GPIO_IDR_IDR15 ((u16)0x8000) /* Port input data, bit 15 */
1874 
1875 
1876 /******************* Bit definition for GPIO_ODR register *******************/
1877 #define GPIO_ODR_ODR0 ((u16)0x0001) /* Port output data, bit 0 */
1878 #define GPIO_ODR_ODR1 ((u16)0x0002) /* Port output data, bit 1 */
1879 #define GPIO_ODR_ODR2 ((u16)0x0004) /* Port output data, bit 2 */
1880 #define GPIO_ODR_ODR3 ((u16)0x0008) /* Port output data, bit 3 */
1881 #define GPIO_ODR_ODR4 ((u16)0x0010) /* Port output data, bit 4 */
1882 #define GPIO_ODR_ODR5 ((u16)0x0020) /* Port output data, bit 5 */
1883 #define GPIO_ODR_ODR6 ((u16)0x0040) /* Port output data, bit 6 */
1884 #define GPIO_ODR_ODR7 ((u16)0x0080) /* Port output data, bit 7 */
1885 #define GPIO_ODR_ODR8 ((u16)0x0100) /* Port output data, bit 8 */
1886 #define GPIO_ODR_ODR9 ((u16)0x0200) /* Port output data, bit 9 */
1887 #define GPIO_ODR_ODR10 ((u16)0x0400) /* Port output data, bit 10 */
1888 #define GPIO_ODR_ODR11 ((u16)0x0800) /* Port output data, bit 11 */
1889 #define GPIO_ODR_ODR12 ((u16)0x1000) /* Port output data, bit 12 */
1890 #define GPIO_ODR_ODR13 ((u16)0x2000) /* Port output data, bit 13 */
1891 #define GPIO_ODR_ODR14 ((u16)0x4000) /* Port output data, bit 14 */
1892 #define GPIO_ODR_ODR15 ((u16)0x8000) /* Port output data, bit 15 */
1893 
1894 
1895 /****************** Bit definition for GPIO_BSRR register *******************/
1896 #define GPIO_BSRR_BS0 ((u32)0x00000001) /* Port x Set bit 0 */
1897 #define GPIO_BSRR_BS1 ((u32)0x00000002) /* Port x Set bit 1 */
1898 #define GPIO_BSRR_BS2 ((u32)0x00000004) /* Port x Set bit 2 */
1899 #define GPIO_BSRR_BS3 ((u32)0x00000008) /* Port x Set bit 3 */
1900 #define GPIO_BSRR_BS4 ((u32)0x00000010) /* Port x Set bit 4 */
1901 #define GPIO_BSRR_BS5 ((u32)0x00000020) /* Port x Set bit 5 */
1902 #define GPIO_BSRR_BS6 ((u32)0x00000040) /* Port x Set bit 6 */
1903 #define GPIO_BSRR_BS7 ((u32)0x00000080) /* Port x Set bit 7 */
1904 #define GPIO_BSRR_BS8 ((u32)0x00000100) /* Port x Set bit 8 */
1905 #define GPIO_BSRR_BS9 ((u32)0x00000200) /* Port x Set bit 9 */
1906 #define GPIO_BSRR_BS10 ((u32)0x00000400) /* Port x Set bit 10 */
1907 #define GPIO_BSRR_BS11 ((u32)0x00000800) /* Port x Set bit 11 */
1908 #define GPIO_BSRR_BS12 ((u32)0x00001000) /* Port x Set bit 12 */
1909 #define GPIO_BSRR_BS13 ((u32)0x00002000) /* Port x Set bit 13 */
1910 #define GPIO_BSRR_BS14 ((u32)0x00004000) /* Port x Set bit 14 */
1911 #define GPIO_BSRR_BS15 ((u32)0x00008000) /* Port x Set bit 15 */
1912 
1913 #define GPIO_BSRR_BR0 ((u32)0x00010000) /* Port x Reset bit 0 */
1914 #define GPIO_BSRR_BR1 ((u32)0x00020000) /* Port x Reset bit 1 */
1915 #define GPIO_BSRR_BR2 ((u32)0x00040000) /* Port x Reset bit 2 */
1916 #define GPIO_BSRR_BR3 ((u32)0x00080000) /* Port x Reset bit 3 */
1917 #define GPIO_BSRR_BR4 ((u32)0x00100000) /* Port x Reset bit 4 */
1918 #define GPIO_BSRR_BR5 ((u32)0x00200000) /* Port x Reset bit 5 */
1919 #define GPIO_BSRR_BR6 ((u32)0x00400000) /* Port x Reset bit 6 */
1920 #define GPIO_BSRR_BR7 ((u32)0x00800000) /* Port x Reset bit 7 */
1921 #define GPIO_BSRR_BR8 ((u32)0x01000000) /* Port x Reset bit 8 */
1922 #define GPIO_BSRR_BR9 ((u32)0x02000000) /* Port x Reset bit 9 */
1923 #define GPIO_BSRR_BR10 ((u32)0x04000000) /* Port x Reset bit 10 */
1924 #define GPIO_BSRR_BR11 ((u32)0x08000000) /* Port x Reset bit 11 */
1925 #define GPIO_BSRR_BR12 ((u32)0x10000000) /* Port x Reset bit 12 */
1926 #define GPIO_BSRR_BR13 ((u32)0x20000000) /* Port x Reset bit 13 */
1927 #define GPIO_BSRR_BR14 ((u32)0x40000000) /* Port x Reset bit 14 */
1928 #define GPIO_BSRR_BR15 ((u32)0x80000000) /* Port x Reset bit 15 */
1929 
1930 
1931 /******************* Bit definition for GPIO_BRR register *******************/
1932 #define GPIO_BRR_BR0 ((u16)0x0001) /* Port x Reset bit 0 */
1933 #define GPIO_BRR_BR1 ((u16)0x0002) /* Port x Reset bit 1 */
1934 #define GPIO_BRR_BR2 ((u16)0x0004) /* Port x Reset bit 2 */
1935 #define GPIO_BRR_BR3 ((u16)0x0008) /* Port x Reset bit 3 */
1936 #define GPIO_BRR_BR4 ((u16)0x0010) /* Port x Reset bit 4 */
1937 #define GPIO_BRR_BR5 ((u16)0x0020) /* Port x Reset bit 5 */
1938 #define GPIO_BRR_BR6 ((u16)0x0040) /* Port x Reset bit 6 */
1939 #define GPIO_BRR_BR7 ((u16)0x0080) /* Port x Reset bit 7 */
1940 #define GPIO_BRR_BR8 ((u16)0x0100) /* Port x Reset bit 8 */
1941 #define GPIO_BRR_BR9 ((u16)0x0200) /* Port x Reset bit 9 */
1942 #define GPIO_BRR_BR10 ((u16)0x0400) /* Port x Reset bit 10 */
1943 #define GPIO_BRR_BR11 ((u16)0x0800) /* Port x Reset bit 11 */
1944 #define GPIO_BRR_BR12 ((u16)0x1000) /* Port x Reset bit 12 */
1945 #define GPIO_BRR_BR13 ((u16)0x2000) /* Port x Reset bit 13 */
1946 #define GPIO_BRR_BR14 ((u16)0x4000) /* Port x Reset bit 14 */
1947 #define GPIO_BRR_BR15 ((u16)0x8000) /* Port x Reset bit 15 */
1948 
1949 
1950 /****************** Bit definition for GPIO_LCKR register *******************/
1951 #define GPIO_LCKR_LCK0 ((u32)0x00000001) /* Port x Lock bit 0 */
1952 #define GPIO_LCKR_LCK1 ((u32)0x00000002) /* Port x Lock bit 1 */
1953 #define GPIO_LCKR_LCK2 ((u32)0x00000004) /* Port x Lock bit 2 */
1954 #define GPIO_LCKR_LCK3 ((u32)0x00000008) /* Port x Lock bit 3 */
1955 #define GPIO_LCKR_LCK4 ((u32)0x00000010) /* Port x Lock bit 4 */
1956 #define GPIO_LCKR_LCK5 ((u32)0x00000020) /* Port x Lock bit 5 */
1957 #define GPIO_LCKR_LCK6 ((u32)0x00000040) /* Port x Lock bit 6 */
1958 #define GPIO_LCKR_LCK7 ((u32)0x00000080) /* Port x Lock bit 7 */
1959 #define GPIO_LCKR_LCK8 ((u32)0x00000100) /* Port x Lock bit 8 */
1960 #define GPIO_LCKR_LCK9 ((u32)0x00000200) /* Port x Lock bit 9 */
1961 #define GPIO_LCKR_LCK10 ((u32)0x00000400) /* Port x Lock bit 10 */
1962 #define GPIO_LCKR_LCK11 ((u32)0x00000800) /* Port x Lock bit 11 */
1963 #define GPIO_LCKR_LCK12 ((u32)0x00001000) /* Port x Lock bit 12 */
1964 #define GPIO_LCKR_LCK13 ((u32)0x00002000) /* Port x Lock bit 13 */
1965 #define GPIO_LCKR_LCK14 ((u32)0x00004000) /* Port x Lock bit 14 */
1966 #define GPIO_LCKR_LCK15 ((u32)0x00008000) /* Port x Lock bit 15 */
1967 #define GPIO_LCKR_LCKK ((u32)0x00010000) /* Lock key */
1968 
1969 
1970 /*----------------------------------------------------------------------------*/
1971 
1972 
1973 /****************** Bit definition for AFIO_EVCR register *******************/
1974 #define AFIO_EVCR_PIN ((u8)0x0F) /* PIN[3:0] bits (Pin selection) */
1975 #define AFIO_EVCR_PIN_0 ((u8)0x01) /* Bit 0 */
1976 #define AFIO_EVCR_PIN_1 ((u8)0x02) /* Bit 1 */
1977 #define AFIO_EVCR_PIN_2 ((u8)0x04) /* Bit 2 */
1978 #define AFIO_EVCR_PIN_3 ((u8)0x08) /* Bit 3 */
1979 
1980 /* PIN configuration */
1981 #define AFIO_EVCR_PIN_PX0 ((u8)0x00) /* Pin 0 selected */
1982 #define AFIO_EVCR_PIN_PX1 ((u8)0x01) /* Pin 1 selected */
1983 #define AFIO_EVCR_PIN_PX2 ((u8)0x02) /* Pin 2 selected */
1984 #define AFIO_EVCR_PIN_PX3 ((u8)0x03) /* Pin 3 selected */
1985 #define AFIO_EVCR_PIN_PX4 ((u8)0x04) /* Pin 4 selected */
1986 #define AFIO_EVCR_PIN_PX5 ((u8)0x05) /* Pin 5 selected */
1987 #define AFIO_EVCR_PIN_PX6 ((u8)0x06) /* Pin 6 selected */
1988 #define AFIO_EVCR_PIN_PX7 ((u8)0x07) /* Pin 7 selected */
1989 #define AFIO_EVCR_PIN_PX8 ((u8)0x08) /* Pin 8 selected */
1990 #define AFIO_EVCR_PIN_PX9 ((u8)0x09) /* Pin 9 selected */
1991 #define AFIO_EVCR_PIN_PX10 ((u8)0x0A) /* Pin 10 selected */
1992 #define AFIO_EVCR_PIN_PX11 ((u8)0x0B) /* Pin 11 selected */
1993 #define AFIO_EVCR_PIN_PX12 ((u8)0x0C) /* Pin 12 selected */
1994 #define AFIO_EVCR_PIN_PX13 ((u8)0x0D) /* Pin 13 selected */
1995 #define AFIO_EVCR_PIN_PX14 ((u8)0x0E) /* Pin 14 selected */
1996 #define AFIO_EVCR_PIN_PX15 ((u8)0x0F) /* Pin 15 selected */
1997 
1998 #define AFIO_EVCR_PORT ((u8)0x70) /* PORT[2:0] bits (Port selection) */
1999 #define AFIO_EVCR_PORT_0 ((u8)0x10) /* Bit 0 */
2000 #define AFIO_EVCR_PORT_1 ((u8)0x20) /* Bit 1 */
2001 #define AFIO_EVCR_PORT_2 ((u8)0x40) /* Bit 2 */
2002 
2003 /* PORT configuration */
2004 #define AFIO_EVCR_PORT_PA ((u8)0x00) /* Port A selected */
2005 #define AFIO_EVCR_PORT_PB ((u8)0x10) /* Port B selected */
2006 #define AFIO_EVCR_PORT_PC ((u8)0x20) /* Port C selected */
2007 #define AFIO_EVCR_PORT_PD ((u8)0x30) /* Port D selected */
2008 #define AFIO_EVCR_PORT_PE ((u8)0x40) /* Port E selected */
2009 
2010 #define AFIO_EVCR_EVOE ((u8)0x80) /* Event Output Enable */
2011 
2012 
2013 /****************** Bit definition for AFIO_MAPR register *******************/
2014 #define AFIO_MAPR_SPI1 _REMAP ((u32)0x00000001) /* SPI1 remapping */
2015 #define AFIO_MAPR_I2C1_REMAP ((u32)0x00000002) /* I2C1 remapping */
2016 #define AFIO_MAPR_USART1_REMAP ((u32)0x00000004) /* USART1 remapping */
2017 #define AFIO_MAPR_USART2_REMAP ((u32)0x00000008) /* USART2 remapping */
2018 
2019 #define AFIO_MAPR_USART3_REMAP ((u32)0x00000030) /* USART3_REMAP[1:0] bits (USART3 remapping) */
2020 #define AFIO_MAPR_USART3_REMAP_0 ((u32)0x00000010) /* Bit 0 */
2021 #define AFIO_MAPR_USART3_REMAP_1 ((u32)0x00000020) /* Bit 1 */
2022 
2023 /* USART3_REMAP configuration */
2024 #define AFIO_MAPR_USART3_REMAP_NOREMAP ((u32)0x00000000) /* No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
2025 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((u32)0x00000010) /* Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
2026 #define AFIO_MAPR_USART3_REMAP_FULLREMAP ((u32)0x00000030) /* Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
2027 
2028 #define AFIO_MAPR_TIM1_REMAP ((u32)0x000000C0) /* TIM1_REMAP[1:0] bits (TIM1 remapping) */
2029 #define AFIO_MAPR_TIM1_REMAP_0 ((u32)0x00000040) /* Bit 0 */
2030 #define AFIO_MAPR_TIM1_REMAP_1 ((u32)0x00000080) /* Bit 1 */
2031 
2032 /* TIM1_REMAP configuration */
2033 #define AFIO_MAPR_TIM1_REMAP_NOREMAP ((u32)0x00000000) /* No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
2034 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((u32)0x00000040) /* Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
2035 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((u32)0x000000C0) /* Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
2036 
2037 #define AFIO_MAPR_TIM2_REMAP ((u32)0x00000300) /* TIM2_REMAP[1:0] bits (TIM2 remapping) */
2038 #define AFIO_MAPR_TIM2_REMAP_0 ((u32)0x00000100) /* Bit 0 */
2039 #define AFIO_MAPR_TIM2_REMAP_1 ((u32)0x00000200) /* Bit 1 */
2040 
2041 /* TIM2_REMAP configuration */
2042 #define AFIO_MAPR_TIM2_REMAP_NOREMAP ((u32)0x00000000) /* No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
2043 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((u32)0x00000100) /* Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
2044 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((u32)0x00000200) /* Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
2045 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((u32)0x00000300) /* Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
2046 
2047 #define AFIO_MAPR_TIM3_REMAP ((u32)0x00000C00) /* TIM3_REMAP[1:0] bits (TIM3 remapping) */
2048 #define AFIO_MAPR_TIM3_REMAP_0 ((u32)0x00000400) /* Bit 0 */
2049 #define AFIO_MAPR_TIM3_REMAP_1 ((u32)0x00000800) /* Bit 1 */
2050 
2051 /* TIM3_REMAP configuration */
2052 #define AFIO_MAPR_TIM3_REMAP_NOREMAP ((u32)0x00000000) /* No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
2053 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((u32)0x00000800) /* Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
2054 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((u32)0x00000C00) /* Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
2055 
2056 #define AFIO_MAPR_TIM4_REMAP ((u32)0x00001000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
2057 
2058 #define AFIO_MAPR_CAN_REMAP ((u32)0x00006000) /* CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
2059 #define AFIO_MAPR_CAN_REMAP_0 ((u32)0x00002000) /* Bit 0 */
2060 #define AFIO_MAPR_CAN_REMAP_1 ((u32)0x00004000) /* Bit 1 */
2061 
2062 /* CAN_REMAP configuration */
2063 #define AFIO_MAPR_CAN_REMAP_REMAP1 ((u32)0x00000000) /* CANRX mapped to PA11, CANTX mapped to PA12 */
2064 #define AFIO_MAPR_CAN_REMAP_REMAP2 ((u32)0x00004000) /* CANRX mapped to PB8, CANTX mapped to PB9 */
2065 #define AFIO_MAPR_CAN_REMAP_REMAP3 ((u32)0x00006000) /* CANRX mapped to PD0, CANTX mapped to PD1 */
2066 
2067 #define AFIO_MAPR_PD01_REMAP ((u32)0x00008000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
2068 #define AFIO_MAPR_TIM5CH4_IREMAP ((u32)0x00010000) /* TIM5 Channel4 Internal Remap */
2069 #define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((u32)0x00020000) /* ADC 1 External Trigger Injected Conversion remapping */
2070 #define AFIO_MAPR_ADC1_ETRGREG_REMAP ((u32)0x00040000) /* ADC 1 External Trigger Regular Conversion remapping */
2071 #define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((u32)0x00080000) /* ADC 2 External Trigger Injected Conversion remapping */
2072 #define AFIO_MAPR_ADC2_ETRGREG_REMAP ((u32)0x00100000) /* ADC 2 External Trigger Regular Conversion remapping */
2073 
2074 #define AFIO_MAPR_SWJ_CFG ((u32)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
2075 #define AFIO_MAPR_SWJ_CFG_0 ((u32)0x01000000) /* Bit 0 */
2076 #define AFIO_MAPR_SWJ_CFG_1 ((u32)0x02000000) /* Bit 1 */
2077 #define AFIO_MAPR_SWJ_CFG_2 ((u32)0x04000000) /* Bit 2 */
2078 
2079 /* SWJ_CFG configuration */
2080 #define AFIO_MAPR_SWJ_CFG_RESET ((u32)0x00000000) /* Full SWJ (JTAG-DP + SW-DP) : Reset State */
2081 #define AFIO_MAPR_SWJ_CFG_NOJNTRST ((u32)0x01000000) /* Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
2082 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((u32)0x02000000) /* JTAG-DP Disabled and SW-DP Enabled */
2083 #define AFIO_MAPR_SWJ_CFG_DISABLE ((u32)0x04000000) /* JTAG-DP Disabled and SW-DP Disabled */
2084 
2085 
2086 /***************** Bit definition for AFIO_EXTICR1 register *****************/
2087 #define AFIO_EXTICR1_EXTI0 ((u16)0x000F) /* EXTI 0 configuration */
2088 #define AFIO_EXTICR1_EXTI1 ((u16)0x00F0) /* EXTI 1 configuration */
2089 #define AFIO_EXTICR1_EXTI2 ((u16)0x0F00) /* EXTI 2 configuration */
2090 #define AFIO_EXTICR1_EXTI3 ((u16)0xF000) /* EXTI 3 configuration */
2091 
2092 /* EXTI0 configuration */
2093 #define AFIO_EXTICR1_EXTI0_PA ((u16)0x0000) /* PA[0] pin */
2094 #define AFIO_EXTICR1_EXTI0_PB ((u16)0x0001) /* PB[0] pin */
2095 #define AFIO_EXTICR1_EXTI0_PC ((u16)0x0002) /* PC[0] pin */
2096 #define AFIO_EXTICR1_EXTI0_PD ((u16)0x0003) /* PD[0] pin */
2097 #define AFIO_EXTICR1_EXTI0_PE ((u16)0x0004) /* PE[0] pin */
2098 #define AFIO_EXTICR1_EXTI0_PF ((u16)0x0005) /* PF[0] pin */
2099 #define AFIO_EXTICR1_EXTI0_PG ((u16)0x0006) /* PG[0] pin */
2100 
2101 /* EXTI1 configuration */
2102 #define AFIO_EXTICR1_EXTI1_PA ((u16)0x0000) /* PA[1] pin */
2103 #define AFIO_EXTICR1_EXTI1_PB ((u16)0x0010) /* PB[1] pin */
2104 #define AFIO_EXTICR1_EXTI1_PC ((u16)0x0020) /* PC[1] pin */
2105 #define AFIO_EXTICR1_EXTI1_PD ((u16)0x0030) /* PD[1] pin */
2106 #define AFIO_EXTICR1_EXTI1_PE ((u16)0x0040) /* PE[1] pin */
2107 #define AFIO_EXTICR1_EXTI1_PF ((u16)0x0050) /* PF[1] pin */
2108 #define AFIO_EXTICR1_EXTI1_PG ((u16)0x0060) /* PG[1] pin */
2109 
2110 /* EXTI2 configuration */
2111 #define AFIO_EXTICR1_EXTI2_PA ((u16)0x0000) /* PA[2] pin */
2112 #define AFIO_EXTICR1_EXTI2_PB ((u16)0x0100) /* PB[2] pin */
2113 #define AFIO_EXTICR1_EXTI2_PC ((u16)0x0200) /* PC[2] pin */
2114 #define AFIO_EXTICR1_EXTI2_PD ((u16)0x0300) /* PD[2] pin */
2115 #define AFIO_EXTICR1_EXTI2_PE ((u16)0x0400) /* PE[2] pin */
2116 #define AFIO_EXTICR1_EXTI2_PF ((u16)0x0500) /* PF[2] pin */
2117 #define AFIO_EXTICR1_EXTI2_PG ((u16)0x0600) /* PG[2] pin */
2118 
2119 /* EXTI3 configuration */
2120 #define AFIO_EXTICR1_EXTI3_PA ((u16)0x0000) /* PA[3] pin */
2121 #define AFIO_EXTICR1_EXTI3_PB ((u16)0x1000) /* PB[3] pin */
2122 #define AFIO_EXTICR1_EXTI3_PC ((u16)0x2000) /* PC[3] pin */
2123 #define AFIO_EXTICR1_EXTI3_PD ((u16)0x3000) /* PD[3] pin */
2124 #define AFIO_EXTICR1_EXTI3_PE ((u16)0x4000) /* PE[3] pin */
2125 #define AFIO_EXTICR1_EXTI3_PF ((u16)0x5000) /* PF[3] pin */
2126 #define AFIO_EXTICR1_EXTI3_PG ((u16)0x6000) /* PG[3] pin */
2127 
2128 
2129 /***************** Bit definition for AFIO_EXTICR2 register *****************/
2130 #define AFIO_EXTICR2_EXTI4 ((u16)0x000F) /* EXTI 4 configuration */
2131 #define AFIO_EXTICR2_EXTI5 ((u16)0x00F0) /* EXTI 5 configuration */
2132 #define AFIO_EXTICR2_EXTI6 ((u16)0x0F00) /* EXTI 6 configuration */
2133 #define AFIO_EXTICR2_EXTI7 ((u16)0xF000) /* EXTI 7 configuration */
2134 
2135 /* EXTI4 configuration */
2136 #define AFIO_EXTICR2_EXTI4_PA ((u16)0x0000) /* PA[4] pin */
2137 #define AFIO_EXTICR2_EXTI4_PB ((u16)0x0001) /* PB[4] pin */
2138 #define AFIO_EXTICR2_EXTI4_PC ((u16)0x0002) /* PC[4] pin */
2139 #define AFIO_EXTICR2_EXTI4_PD ((u16)0x0003) /* PD[4] pin */
2140 #define AFIO_EXTICR2_EXTI4_PE ((u16)0x0004) /* PE[4] pin */
2141 #define AFIO_EXTICR2_EXTI4_PF ((u16)0x0005) /* PF[4] pin */
2142 #define AFIO_EXTICR2_EXTI4_PG ((u16)0x0006) /* PG[4] pin */
2143 
2144 /* EXTI5 configuration */
2145 #define AFIO_EXTICR2_EXTI5_PA ((u16)0x0000) /* PA[5] pin */
2146 #define AFIO_EXTICR2_EXTI5_PB ((u16)0x0010) /* PB[5] pin */
2147 #define AFIO_EXTICR2_EXTI5_PC ((u16)0x0020) /* PC[5] pin */
2148 #define AFIO_EXTICR2_EXTI5_PD ((u16)0x0030) /* PD[5] pin */
2149 #define AFIO_EXTICR2_EXTI5_PE ((u16)0x0040) /* PE[5] pin */
2150 #define AFIO_EXTICR2_EXTI5_PF ((u16)0x0050) /* PF[5] pin */
2151 #define AFIO_EXTICR2_EXTI5_PG ((u16)0x0060) /* PG[5] pin */
2152 
2153 /* EXTI6 configuration */
2154 #define AFIO_EXTICR2_EXTI6_PA ((u16)0x0000) /* PA[6] pin */
2155 #define AFIO_EXTICR2_EXTI6_PB ((u16)0x0100) /* PB[6] pin */
2156 #define AFIO_EXTICR2_EXTI6_PC ((u16)0x0200) /* PC[6] pin */
2157 #define AFIO_EXTICR2_EXTI6_PD ((u16)0x0300) /* PD[6] pin */
2158 #define AFIO_EXTICR2_EXTI6_PE ((u16)0x0400) /* PE[6] pin */
2159 #define AFIO_EXTICR2_EXTI6_PF ((u16)0x0500) /* PF[6] pin */
2160 #define AFIO_EXTICR2_EXTI6_PG ((u16)0x0600) /* PG[6] pin */
2161 
2162 /* EXTI7 configuration */
2163 #define AFIO_EXTICR2_EXTI7_PA ((u16)0x0000) /* PA[7] pin */
2164 #define AFIO_EXTICR2_EXTI7_PB ((u16)0x1000) /* PB[7] pin */
2165 #define AFIO_EXTICR2_EXTI7_PC ((u16)0x2000) /* PC[7] pin */
2166 #define AFIO_EXTICR2_EXTI7_PD ((u16)0x3000) /* PD[7] pin */
2167 #define AFIO_EXTICR2_EXTI7_PE ((u16)0x4000) /* PE[7] pin */
2168 #define AFIO_EXTICR2_EXTI7_PF ((u16)0x5000) /* PF[7] pin */
2169 #define AFIO_EXTICR2_EXTI7_PG ((u16)0x6000) /* PG[7] pin */
2170 
2171 
2172 /***************** Bit definition for AFIO_EXTICR3 register *****************/
2173 #define AFIO_EXTICR3_EXTI8 ((u16)0x000F) /* EXTI 8 configuration */
2174 #define AFIO_EXTICR3_EXTI9 ((u16)0x00F0) /* EXTI 9 configuration */
2175 #define AFIO_EXTICR3_EXTI10 ((u16)0x0F00) /* EXTI 10 configuration */
2176 #define AFIO_EXTICR3_EXTI11 ((u16)0xF000) /* EXTI 11 configuration */
2177 
2178 /* EXTI8 configuration */
2179 #define AFIO_EXTICR3_EXTI8_PA ((u16)0x0000) /* PA[8] pin */
2180 #define AFIO_EXTICR3_EXTI8_PB ((u16)0x0001) /* PB[8] pin */
2181 #define AFIO_EXTICR3_EXTI8_PC ((u16)0x0002) /* PC[8] pin */
2182 #define AFIO_EXTICR3_EXTI8_PD ((u16)0x0003) /* PD[8] pin */
2183 #define AFIO_EXTICR3_EXTI8_PE ((u16)0x0004) /* PE[8] pin */
2184 #define AFIO_EXTICR3_EXTI8_PF ((u16)0x0005) /* PF[8] pin */
2185 #define AFIO_EXTICR3_EXTI8_PG ((u16)0x0006) /* PG[8] pin */
2186 
2187 /* EXTI9 configuration */
2188 #define AFIO_EXTICR3_EXTI9_PA ((u16)0x0000) /* PA[9] pin */
2189 #define AFIO_EXTICR3_EXTI9_PB ((u16)0x0010) /* PB[9] pin */
2190 #define AFIO_EXTICR3_EXTI9_PC ((u16)0x0020) /* PC[9] pin */
2191 #define AFIO_EXTICR3_EXTI9_PD ((u16)0x0030) /* PD[9] pin */
2192 #define AFIO_EXTICR3_EXTI9_PE ((u16)0x0040) /* PE[9] pin */
2193 #define AFIO_EXTICR3_EXTI9_PF ((u16)0x0050) /* PF[9] pin */
2194 #define AFIO_EXTICR3_EXTI9_PG ((u16)0x0060) /* PG[9] pin */
2195 
2196 /* EXTI10 configuration */
2197 #define AFIO_EXTICR3_EXTI10_PA ((u16)0x0000) /* PA[10] pin */
2198 #define AFIO_EXTICR3_EXTI10_PB ((u16)0x0100) /* PB[10] pin */
2199 #define AFIO_EXTICR3_EXTI10_PC ((u16)0x0200) /* PC[10] pin */
2200 #define AFIO_EXTICR3_EXTI10_PD ((u16)0x0300) /* PD[10] pin */
2201 #define AFIO_EXTICR3_EXTI10_PE ((u16)0x0400) /* PE[10] pin */
2202 #define AFIO_EXTICR3_EXTI10_PF ((u16)0x0500) /* PF[10] pin */
2203 #define AFIO_EXTICR3_EXTI10_PG ((u16)0x0600) /* PG[10] pin */
2204 
2205 /* EXTI11 configuration */
2206 #define AFIO_EXTICR3_EXTI11_PA ((u16)0x0000) /* PA[11] pin */
2207 #define AFIO_EXTICR3_EXTI11_PB ((u16)0x1000) /* PB[11] pin */
2208 #define AFIO_EXTICR3_EXTI11_PC ((u16)0x2000) /* PC[11] pin */
2209 #define AFIO_EXTICR3_EXTI11_PD ((u16)0x3000) /* PD[11] pin */
2210 #define AFIO_EXTICR3_EXTI11_PE ((u16)0x4000) /* PE[11] pin */
2211 #define AFIO_EXTICR3_EXTI11_PF ((u16)0x5000) /* PF[11] pin */
2212 #define AFIO_EXTICR3_EXTI11_PG ((u16)0x6000) /* PG[11] pin */
2213 
2214 
2215 /***************** Bit definition for AFIO_EXTICR4 register *****************/
2216 #define AFIO_EXTICR4_EXTI12 ((u16)0x000F) /* EXTI 12 configuration */
2217 #define AFIO_EXTICR4_EXTI13 ((u16)0x00F0) /* EXTI 13 configuration */
2218 #define AFIO_EXTICR4_EXTI14 ((u16)0x0F00) /* EXTI 14 configuration */
2219 #define AFIO_EXTICR4_EXTI15 ((u16)0xF000) /* EXTI 15 configuration */
2220 
2221 /* EXTI12 configuration */
2222 #define AFIO_EXTICR4_EXTI12_PA ((u16)0x0000) /* PA[12] pin */
2223 #define AFIO_EXTICR4_EXTI12_PB ((u16)0x0001) /* PB[12] pin */
2224 #define AFIO_EXTICR4_EXTI12_PC ((u16)0x0002) /* PC[12] pin */
2225 #define AFIO_EXTICR4_EXTI12_PD ((u16)0x0003) /* PD[12] pin */
2226 #define AFIO_EXTICR4_EXTI12_PE ((u16)0x0004) /* PE[12] pin */
2227 #define AFIO_EXTICR4_EXTI12_PF ((u16)0x0005) /* PF[12] pin */
2228 #define AFIO_EXTICR4_EXTI12_PG ((u16)0x0006) /* PG[12] pin */
2229 
2230 /* EXTI13 configuration */
2231 #define AFIO_EXTICR4_EXTI13_PA ((u16)0x0000) /* PA[13] pin */
2232 #define AFIO_EXTICR4_EXTI13_PB ((u16)0x0010) /* PB[13] pin */
2233 #define AFIO_EXTICR4_EXTI13_PC ((u16)0x0020) /* PC[13] pin */
2234 #define AFIO_EXTICR4_EXTI13_PD ((u16)0x0030) /* PD[13] pin */
2235 #define AFIO_EXTICR4_EXTI13_PE ((u16)0x0040) /* PE[13] pin */
2236 #define AFIO_EXTICR4_EXTI13_PF ((u16)0x0050) /* PF[13] pin */
2237 #define AFIO_EXTICR4_EXTI13_PG ((u16)0x0060) /* PG[13] pin */
2238 
2239 /* EXTI14 configuration */
2240 #define AFIO_EXTICR4_EXTI14_PA ((u16)0x0000) /* PA[14] pin */
2241 #define AFIO_EXTICR4_EXTI14_PB ((u16)0x0100) /* PB[14] pin */
2242 #define AFIO_EXTICR4_EXTI14_PC ((u16)0x0200) /* PC[14] pin */
2243 #define AFIO_EXTICR4_EXTI14_PD ((u16)0x0300) /* PD[14] pin */
2244 #define AFIO_EXTICR4_EXTI14_PE ((u16)0x0400) /* PE[14] pin */
2245 #define AFIO_EXTICR4_EXTI14_PF ((u16)0x0500) /* PF[14] pin */
2246 #define AFIO_EXTICR4_EXTI14_PG ((u16)0x0600) /* PG[14] pin */
2247 
2248 /* EXTI15 configuration */
2249 #define AFIO_EXTICR4_EXTI15_PA ((u16)0x0000) /* PA[15] pin */
2250 #define AFIO_EXTICR4_EXTI15_PB ((u16)0x1000) /* PB[15] pin */
2251 #define AFIO_EXTICR4_EXTI15_PC ((u16)0x2000) /* PC[15] pin */
2252 #define AFIO_EXTICR4_EXTI15_PD ((u16)0x3000) /* PD[15] pin */
2253 #define AFIO_EXTICR4_EXTI15_PE ((u16)0x4000) /* PE[15] pin */
2254 #define AFIO_EXTICR4_EXTI15_PF ((u16)0x5000) /* PF[15] pin */
2255 #define AFIO_EXTICR4_EXTI15_PG ((u16)0x6000) /* PG[15] pin */
2256 
2257 
2258 
2259 /******************************************************************************/
2260 /* */
2261 /* SystemTick */
2262 /* */
2263 /******************************************************************************/
2264 
2265 /***************** Bit definition for SysTick_CTRL register *****************/
2266 #define SysTick_CTRL_ENABLE ((u32)0x00000001) /* Counter enable */
2267 #define SysTick_CTRL_TICKINT ((u32)0x00000002) /* Counting down to 0 pends the SysTick handler */
2268 #define SysTick_CTRL_CLKSOURCE ((u32)0x00000004) /* Clock source */
2269 #define SysTick_CTRL_COUNTFLAG ((u32)0x00010000) /* Count Flag */
2270 
2271 
2272 /***************** Bit definition for SysTick_LOAD register *****************/
2273 #define SysTick_LOAD_RELOAD ((u32)0x00FFFFFF) /* Value to load into the SysTick Current Value Register when the counter reaches 0 */
2274 
2275 
2276 /***************** Bit definition for SysTick_VAL register ******************/
2277 #define SysTick_VAL_CURRENT ((u32)0x00FFFFFF) /* Current value at the time the register is accessed */
2278 
2279 
2280 /***************** Bit definition for SysTick_CALIB register ****************/
2281 #define SysTick_CALIB_TENMS ((u32)0x00FFFFFF) /* Reload value to use for 10ms timing */
2282 #define SysTick_CALIB_SKEW ((u32)0x40000000) /* Calibration value is not exactly 10 ms */
2283 #define SysTick_CALIB_NOREF ((u32)0x80000000) /* The reference clock is not provided */
2284 
2285 
2286 
2287 /******************************************************************************/
2288 /* */
2289 /* Nested Vectored Interrupt Controller */
2290 /* */
2291 /******************************************************************************/
2292 
2293 /****************** Bit definition for NVIC_ISER register *******************/
2294 #define NVIC_ISER_SETENA ((u32)0xFFFFFFFF) /* Interrupt set enable bits */
2295 #define NVIC_ISER_SETENA_0 ((u32)0x00000001) /* bit 0 */
2296 #define NVIC_ISER_SETENA_1 ((u32)0x00000002) /* bit 1 */
2297 #define NVIC_ISER_SETENA_2 ((u32)0x00000004) /* bit 2 */
2298 #define NVIC_ISER_SETENA_3 ((u32)0x00000008) /* bit 3 */
2299 #define NVIC_ISER_SETENA_4 ((u32)0x00000010) /* bit 4 */
2300 #define NVIC_ISER_SETENA_5 ((u32)0x00000020) /* bit 5 */
2301 #define NVIC_ISER_SETENA_6 ((u32)0x00000040) /* bit 6 */
2302 #define NVIC_ISER_SETENA_7 ((u32)0x00000080) /* bit 7 */
2303 #define NVIC_ISER_SETENA_8 ((u32)0x00000100) /* bit 8 */
2304 #define NVIC_ISER_SETENA_9 ((u32)0x00000200) /* bit 9 */
2305 #define NVIC_ISER_SETENA_10 ((u32)0x00000400) /* bit 10 */
2306 #define NVIC_ISER_SETENA_11 ((u32)0x00000800) /* bit 11 */
2307 #define NVIC_ISER_SETENA_12 ((u32)0x00001000) /* bit 12 */
2308 #define NVIC_ISER_SETENA_13 ((u32)0x00002000) /* bit 13 */
2309 #define NVIC_ISER_SETENA_14 ((u32)0x00004000) /* bit 14 */
2310 #define NVIC_ISER_SETENA_15 ((u32)0x00008000) /* bit 15 */
2311 #define NVIC_ISER_SETENA_16 ((u32)0x00010000) /* bit 16 */
2312 #define NVIC_ISER_SETENA_17 ((u32)0x00020000) /* bit 17 */
2313 #define NVIC_ISER_SETENA_18 ((u32)0x00040000) /* bit 18 */
2314 #define NVIC_ISER_SETENA_19 ((u32)0x00080000) /* bit 19 */
2315 #define NVIC_ISER_SETENA_20 ((u32)0x00100000) /* bit 20 */
2316 #define NVIC_ISER_SETENA_21 ((u32)0x00200000) /* bit 21 */
2317 #define NVIC_ISER_SETENA_22 ((u32)0x00400000) /* bit 22 */
2318 #define NVIC_ISER_SETENA_23 ((u32)0x00800000) /* bit 23 */
2319 #define NVIC_ISER_SETENA_24 ((u32)0x01000000) /* bit 24 */
2320 #define NVIC_ISER_SETENA_25 ((u32)0x02000000) /* bit 25 */
2321 #define NVIC_ISER_SETENA_26 ((u32)0x04000000) /* bit 26 */
2322 #define NVIC_ISER_SETENA_27 ((u32)0x08000000) /* bit 27 */
2323 #define NVIC_ISER_SETENA_28 ((u32)0x10000000) /* bit 28 */
2324 #define NVIC_ISER_SETENA_29 ((u32)0x20000000) /* bit 29 */
2325 #define NVIC_ISER_SETENA_30 ((u32)0x40000000) /* bit 30 */
2326 #define NVIC_ISER_SETENA_31 ((u32)0x80000000) /* bit 31 */
2327 
2328 
2329 
2330 /****************** Bit definition for NVIC_ICER register *******************/
2331 #define NVIC_ICER_CLRENA ((u32)0xFFFFFFFF) /* Interrupt clear-enable bits */
2332 #define NVIC_ICER_CLRENA_0 ((u32)0x00000001) /* bit 0 */
2333 #define NVIC_ICER_CLRENA_1 ((u32)0x00000002) /* bit 1 */
2334 #define NVIC_ICER_CLRENA_2 ((u32)0x00000004) /* bit 2 */
2335 #define NVIC_ICER_CLRENA_3 ((u32)0x00000008) /* bit 3 */
2336 #define NVIC_ICER_CLRENA_4 ((u32)0x00000010) /* bit 4 */
2337 #define NVIC_ICER_CLRENA_5 ((u32)0x00000020) /* bit 5 */
2338 #define NVIC_ICER_CLRENA_6 ((u32)0x00000040) /* bit 6 */
2339 #define NVIC_ICER_CLRENA_7 ((u32)0x00000080) /* bit 7 */
2340 #define NVIC_ICER_CLRENA_8 ((u32)0x00000100) /* bit 8 */
2341 #define NVIC_ICER_CLRENA_9 ((u32)0x00000200) /* bit 9 */
2342 #define NVIC_ICER_CLRENA_10 ((u32)0x00000400) /* bit 10 */
2343 #define NVIC_ICER_CLRENA_11 ((u32)0x00000800) /* bit 11 */
2344 #define NVIC_ICER_CLRENA_12 ((u32)0x00001000) /* bit 12 */
2345 #define NVIC_ICER_CLRENA_13 ((u32)0x00002000) /* bit 13 */
2346 #define NVIC_ICER_CLRENA_14 ((u32)0x00004000) /* bit 14 */
2347 #define NVIC_ICER_CLRENA_15 ((u32)0x00008000) /* bit 15 */
2348 #define NVIC_ICER_CLRENA_16 ((u32)0x00010000) /* bit 16 */
2349 #define NVIC_ICER_CLRENA_17 ((u32)0x00020000) /* bit 17 */
2350 #define NVIC_ICER_CLRENA_18 ((u32)0x00040000) /* bit 18 */
2351 #define NVIC_ICER_CLRENA_19 ((u32)0x00080000) /* bit 19 */
2352 #define NVIC_ICER_CLRENA_20 ((u32)0x00100000) /* bit 20 */
2353 #define NVIC_ICER_CLRENA_21 ((u32)0x00200000) /* bit 21 */
2354 #define NVIC_ICER_CLRENA_22 ((u32)0x00400000) /* bit 22 */
2355 #define NVIC_ICER_CLRENA_23 ((u32)0x00800000) /* bit 23 */
2356 #define NVIC_ICER_CLRENA_24 ((u32)0x01000000) /* bit 24 */
2357 #define NVIC_ICER_CLRENA_25 ((u32)0x02000000) /* bit 25 */
2358 #define NVIC_ICER_CLRENA_26 ((u32)0x04000000) /* bit 26 */
2359 #define NVIC_ICER_CLRENA_27 ((u32)0x08000000) /* bit 27 */
2360 #define NVIC_ICER_CLRENA_28 ((u32)0x10000000) /* bit 28 */
2361 #define NVIC_ICER_CLRENA_29 ((u32)0x20000000) /* bit 29 */
2362 #define NVIC_ICER_CLRENA_30 ((u32)0x40000000) /* bit 30 */
2363 #define NVIC_ICER_CLRENA_31 ((u32)0x80000000) /* bit 31 */
2364 
2365 
2366 /****************** Bit definition for NVIC_ISPR register *******************/
2367 #define NVIC_ISPR_SETPEND ((u32)0xFFFFFFFF) /* Interrupt set-pending bits */
2368 #define NVIC_ISPR_SETPEND_0 ((u32)0x00000001) /* bit 0 */
2369 #define NVIC_ISPR_SETPEND_1 ((u32)0x00000002) /* bit 1 */
2370 #define NVIC_ISPR_SETPEND_2 ((u32)0x00000004) /* bit 2 */
2371 #define NVIC_ISPR_SETPEND_3 ((u32)0x00000008) /* bit 3 */
2372 #define NVIC_ISPR_SETPEND_4 ((u32)0x00000010) /* bit 4 */
2373 #define NVIC_ISPR_SETPEND_5 ((u32)0x00000020) /* bit 5 */
2374 #define NVIC_ISPR_SETPEND_6 ((u32)0x00000040) /* bit 6 */
2375 #define NVIC_ISPR_SETPEND_7 ((u32)0x00000080) /* bit 7 */
2376 #define NVIC_ISPR_SETPEND_8 ((u32)0x00000100) /* bit 8 */
2377 #define NVIC_ISPR_SETPEND_9 ((u32)0x00000200) /* bit 9 */
2378 #define NVIC_ISPR_SETPEND_10 ((u32)0x00000400) /* bit 10 */
2379 #define NVIC_ISPR_SETPEND_11 ((u32)0x00000800) /* bit 11 */
2380 #define NVIC_ISPR_SETPEND_12 ((u32)0x00001000) /* bit 12 */
2381 #define NVIC_ISPR_SETPEND_13 ((u32)0x00002000) /* bit 13 */
2382 #define NVIC_ISPR_SETPEND_14 ((u32)0x00004000) /* bit 14 */
2383 #define NVIC_ISPR_SETPEND_15 ((u32)0x00008000) /* bit 15 */
2384 #define NVIC_ISPR_SETPEND_16 ((u32)0x00010000) /* bit 16 */
2385 #define NVIC_ISPR_SETPEND_17 ((u32)0x00020000) /* bit 17 */
2386 #define NVIC_ISPR_SETPEND_18 ((u32)0x00040000) /* bit 18 */
2387 #define NVIC_ISPR_SETPEND_19 ((u32)0x00080000) /* bit 19 */
2388 #define NVIC_ISPR_SETPEND_20 ((u32)0x00100000) /* bit 20 */
2389 #define NVIC_ISPR_SETPEND_21 ((u32)0x00200000) /* bit 21 */
2390 #define NVIC_ISPR_SETPEND_22 ((u32)0x00400000) /* bit 22 */
2391 #define NVIC_ISPR_SETPEND_23 ((u32)0x00800000) /* bit 23 */
2392 #define NVIC_ISPR_SETPEND_24 ((u32)0x01000000) /* bit 24 */
2393 #define NVIC_ISPR_SETPEND_25 ((u32)0x02000000) /* bit 25 */
2394 #define NVIC_ISPR_SETPEND_26 ((u32)0x04000000) /* bit 26 */
2395 #define NVIC_ISPR_SETPEND_27 ((u32)0x08000000) /* bit 27 */
2396 #define NVIC_ISPR_SETPEND_28 ((u32)0x10000000) /* bit 28 */
2397 #define NVIC_ISPR_SETPEND_29 ((u32)0x20000000) /* bit 29 */
2398 #define NVIC_ISPR_SETPEND_30 ((u32)0x40000000) /* bit 30 */
2399 #define NVIC_ISPR_SETPEND_31 ((u32)0x80000000) /* bit 31 */
2400 
2401 
2402 /****************** Bit definition for NVIC_ICPR register *******************/
2403 #define NVIC_ICPR_CLRPEND ((u32)0xFFFFFFFF) /* Interrupt clear-pending bits */
2404 #define NVIC_ICPR_CLRPEND_0 ((u32)0x00000001) /* bit 0 */
2405 #define NVIC_ICPR_CLRPEND_1 ((u32)0x00000002) /* bit 1 */
2406 #define NVIC_ICPR_CLRPEND_2 ((u32)0x00000004) /* bit 2 */
2407 #define NVIC_ICPR_CLRPEND_3 ((u32)0x00000008) /* bit 3 */
2408 #define NVIC_ICPR_CLRPEND_4 ((u32)0x00000010) /* bit 4 */
2409 #define NVIC_ICPR_CLRPEND_5 ((u32)0x00000020) /* bit 5 */
2410 #define NVIC_ICPR_CLRPEND_6 ((u32)0x00000040) /* bit 6 */
2411 #define NVIC_ICPR_CLRPEND_7 ((u32)0x00000080) /* bit 7 */
2412 #define NVIC_ICPR_CLRPEND_8 ((u32)0x00000100) /* bit 8 */
2413 #define NVIC_ICPR_CLRPEND_9 ((u32)0x00000200) /* bit 9 */
2414 #define NVIC_ICPR_CLRPEND_10 ((u32)0x00000400) /* bit 10 */
2415 #define NVIC_ICPR_CLRPEND_11 ((u32)0x00000800) /* bit 11 */
2416 #define NVIC_ICPR_CLRPEND_12 ((u32)0x00001000) /* bit 12 */
2417 #define NVIC_ICPR_CLRPEND_13 ((u32)0x00002000) /* bit 13 */
2418 #define NVIC_ICPR_CLRPEND_14 ((u32)0x00004000) /* bit 14 */
2419 #define NVIC_ICPR_CLRPEND_15 ((u32)0x00008000) /* bit 15 */
2420 #define NVIC_ICPR_CLRPEND_16 ((u32)0x00010000) /* bit 16 */
2421 #define NVIC_ICPR_CLRPEND_17 ((u32)0x00020000) /* bit 17 */
2422 #define NVIC_ICPR_CLRPEND_18 ((u32)0x00040000) /* bit 18 */
2423 #define NVIC_ICPR_CLRPEND_19 ((u32)0x00080000) /* bit 19 */
2424 #define NVIC_ICPR_CLRPEND_20 ((u32)0x00100000) /* bit 20 */
2425 #define NVIC_ICPR_CLRPEND_21 ((u32)0x00200000) /* bit 21 */
2426 #define NVIC_ICPR_CLRPEND_22 ((u32)0x00400000) /* bit 22 */
2427 #define NVIC_ICPR_CLRPEND_23 ((u32)0x00800000) /* bit 23 */
2428 #define NVIC_ICPR_CLRPEND_24 ((u32)0x01000000) /* bit 24 */
2429 #define NVIC_ICPR_CLRPEND_25 ((u32)0x02000000) /* bit 25 */
2430 #define NVIC_ICPR_CLRPEND_26 ((u32)0x04000000) /* bit 26 */
2431 #define NVIC_ICPR_CLRPEND_27 ((u32)0x08000000) /* bit 27 */
2432 #define NVIC_ICPR_CLRPEND_28 ((u32)0x10000000) /* bit 28 */
2433 #define NVIC_ICPR_CLRPEND_29 ((u32)0x20000000) /* bit 29 */
2434 #define NVIC_ICPR_CLRPEND_30 ((u32)0x40000000) /* bit 30 */
2435 #define NVIC_ICPR_CLRPEND_31 ((u32)0x80000000) /* bit 31 */
2436 
2437 
2438 /****************** Bit definition for NVIC_IABR register *******************/
2439 #define NVIC_IABR_ACTIVE ((u32)0xFFFFFFFF) /* Interrupt active flags */
2440 #define NVIC_IABR_ACTIVE_0 ((u32)0x00000001) /* bit 0 */
2441 #define NVIC_IABR_ACTIVE_1 ((u32)0x00000002) /* bit 1 */
2442 #define NVIC_IABR_ACTIVE_2 ((u32)0x00000004) /* bit 2 */
2443 #define NVIC_IABR_ACTIVE_3 ((u32)0x00000008) /* bit 3 */
2444 #define NVIC_IABR_ACTIVE_4 ((u32)0x00000010) /* bit 4 */
2445 #define NVIC_IABR_ACTIVE_5 ((u32)0x00000020) /* bit 5 */
2446 #define NVIC_IABR_ACTIVE_6 ((u32)0x00000040) /* bit 6 */
2447 #define NVIC_IABR_ACTIVE_7 ((u32)0x00000080) /* bit 7 */
2448 #define NVIC_IABR_ACTIVE_8 ((u32)0x00000100) /* bit 8 */
2449 #define NVIC_IABR_ACTIVE_9 ((u32)0x00000200) /* bit 9 */
2450 #define NVIC_IABR_ACTIVE_10 ((u32)0x00000400) /* bit 10 */
2451 #define NVIC_IABR_ACTIVE_11 ((u32)0x00000800) /* bit 11 */
2452 #define NVIC_IABR_ACTIVE_12 ((u32)0x00001000) /* bit 12 */
2453 #define NVIC_IABR_ACTIVE_13 ((u32)0x00002000) /* bit 13 */
2454 #define NVIC_IABR_ACTIVE_14 ((u32)0x00004000) /* bit 14 */
2455 #define NVIC_IABR_ACTIVE_15 ((u32)0x00008000) /* bit 15 */
2456 #define NVIC_IABR_ACTIVE_16 ((u32)0x00010000) /* bit 16 */
2457 #define NVIC_IABR_ACTIVE_17 ((u32)0x00020000) /* bit 17 */
2458 #define NVIC_IABR_ACTIVE_18 ((u32)0x00040000) /* bit 18 */
2459 #define NVIC_IABR_ACTIVE_19 ((u32)0x00080000) /* bit 19 */
2460 #define NVIC_IABR_ACTIVE_20 ((u32)0x00100000) /* bit 20 */
2461 #define NVIC_IABR_ACTIVE_21 ((u32)0x00200000) /* bit 21 */
2462 #define NVIC_IABR_ACTIVE_22 ((u32)0x00400000) /* bit 22 */
2463 #define NVIC_IABR_ACTIVE_23 ((u32)0x00800000) /* bit 23 */
2464 #define NVIC_IABR_ACTIVE_24 ((u32)0x01000000) /* bit 24 */
2465 #define NVIC_IABR_ACTIVE_25 ((u32)0x02000000) /* bit 25 */
2466 #define NVIC_IABR_ACTIVE_26 ((u32)0x04000000) /* bit 26 */
2467 #define NVIC_IABR_ACTIVE_27 ((u32)0x08000000) /* bit 27 */
2468 #define NVIC_IABR_ACTIVE_28 ((u32)0x10000000) /* bit 28 */
2469 #define NVIC_IABR_ACTIVE_29 ((u32)0x20000000) /* bit 29 */
2470 #define NVIC_IABR_ACTIVE_30 ((u32)0x40000000) /* bit 30 */
2471 #define NVIC_IABR_ACTIVE_31 ((u32)0x80000000) /* bit 31 */
2472 
2473 
2474 /****************** Bit definition for NVIC_PRI0 register *******************/
2475 #define NVIC_IPR0_PRI_0 ((u32)0x000000FF) /* Priority of interrupt 0 */
2476 #define NVIC_IPR0_PRI_1 ((u32)0x0000FF00) /* Priority of interrupt 1 */
2477 #define NVIC_IPR0_PRI_2 ((u32)0x00FF0000) /* Priority of interrupt 2 */
2478 #define NVIC_IPR0_PRI_3 ((u32)0xFF000000) /* Priority of interrupt 3 */
2479 
2480 
2481 /****************** Bit definition for NVIC_PRI1 register *******************/
2482 #define NVIC_IPR1_PRI_4 ((u32)0x000000FF) /* Priority of interrupt 4 */
2483 #define NVIC_IPR1_PRI_5 ((u32)0x0000FF00) /* Priority of interrupt 5 */
2484 #define NVIC_IPR1_PRI_6 ((u32)0x00FF0000) /* Priority of interrupt 6 */
2485 #define NVIC_IPR1_PRI_7 ((u32)0xFF000000) /* Priority of interrupt 7 */
2486 
2487 
2488 /****************** Bit definition for NVIC_PRI2 register *******************/
2489 #define NVIC_IPR2_PRI_8 ((u32)0x000000FF) /* Priority of interrupt 8 */
2490 #define NVIC_IPR2_PRI_9 ((u32)0x0000FF00) /* Priority of interrupt 9 */
2491 #define NVIC_IPR2_PRI_10 ((u32)0x00FF0000) /* Priority of interrupt 10 */
2492 #define NVIC_IPR2_PRI_11 ((u32)0xFF000000) /* Priority of interrupt 11 */
2493 
2494 
2495 /****************** Bit definition for NVIC_PRI3 register *******************/
2496 #define NVIC_IPR3_PRI_12 ((u32)0x000000FF) /* Priority of interrupt 12 */
2497 #define NVIC_IPR3_PRI_13 ((u32)0x0000FF00) /* Priority of interrupt 13 */
2498 #define NVIC_IPR3_PRI_14 ((u32)0x00FF0000) /* Priority of interrupt 14 */
2499 #define NVIC_IPR3_PRI_15 ((u32)0xFF000000) /* Priority of interrupt 15 */
2500 
2501 
2502 /****************** Bit definition for NVIC_PRI4 register *******************/
2503 #define NVIC_IPR4_PRI_16 ((u32)0x000000FF) /* Priority of interrupt 16 */
2504 #define NVIC_IPR4_PRI_17 ((u32)0x0000FF00) /* Priority of interrupt 17 */
2505 #define NVIC_IPR4_PRI_18 ((u32)0x00FF0000) /* Priority of interrupt 18 */
2506 #define NVIC_IPR4_PRI_19 ((u32)0xFF000000) /* Priority of interrupt 19 */
2507 
2508 
2509 /****************** Bit definition for NVIC_PRI5 register *******************/
2510 #define NVIC_IPR5_PRI_20 ((u32)0x000000FF) /* Priority of interrupt 20 */
2511 #define NVIC_IPR5_PRI_21 ((u32)0x0000FF00) /* Priority of interrupt 21 */
2512 #define NVIC_IPR5_PRI_22 ((u32)0x00FF0000) /* Priority of interrupt 22 */
2513 #define NVIC_IPR5_PRI_23 ((u32)0xFF000000) /* Priority of interrupt 23 */
2514 
2515 
2516 /****************** Bit definition for NVIC_PRI6 register *******************/
2517 #define NVIC_IPR6_PRI_24 ((u32)0x000000FF) /* Priority of interrupt 24 */
2518 #define NVIC_IPR6_PRI_25 ((u32)0x0000FF00) /* Priority of interrupt 25 */
2519 #define NVIC_IPR6_PRI_26 ((u32)0x00FF0000) /* Priority of interrupt 26 */
2520 #define NVIC_IPR6_PRI_27 ((u32)0xFF000000) /* Priority of interrupt 27 */
2521 
2522 
2523 /****************** Bit definition for NVIC_PRI7 register *******************/
2524 #define NVIC_IPR7_PRI_28 ((u32)0x000000FF) /* Priority of interrupt 28 */
2525 #define NVIC_IPR7_PRI_29 ((u32)0x0000FF00) /* Priority of interrupt 29 */
2526 #define NVIC_IPR7_PRI_30 ((u32)0x00FF0000) /* Priority of interrupt 30 */
2527 #define NVIC_IPR7_PRI_31 ((u32)0xFF000000) /* Priority of interrupt 31 */
2528 
2529 
2530 /****************** Bit definition for SCB_CPUID register *******************/
2531 #define SCB_CPUID_REVISION ((u32)0x0000000F) /* Implementation defined revision number */
2532 #define SCB_CPUID_PARTNO ((u32)0x0000FFF0) /* Number of processor within family */
2533 #define SCB_CPUID_Constant ((u32)0x000F0000) /* Reads as 0x0F */
2534 #define SCB_CPUID_VARIANT ((u32)0x00F00000) /* Implementation defined variant number */
2535 #define SCB_CPUID_IMPLEMENTER ((u32)0xFF000000) /* Implementer code. ARM is 0x41 */
2536 
2537 
2538 /******************* Bit definition for SCB_ICSR register *******************/
2539 #define SCB_ICSR_VECTACTIVE ((u32)0x000001FF) /* Active ISR number field */
2540 #define SCB_ICSR_RETTOBASE ((u32)0x00000800) /* All active exceptions minus the IPSR_current_exception yields the empty set */
2541 #define SCB_ICSR_VECTPENDING ((u32)0x003FF000) /* Pending ISR number field */
2542 #define SCB_ICSR_ISRPENDING ((u32)0x00400000) /* Interrupt pending flag */
2543 #define SCB_ICSR_ISRPREEMPT ((u32)0x00800000) /* It indicates that a pending interrupt becomes active in the next running cycle */
2544 #define SCB_ICSR_PENDSTCLR ((u32)0x02000000) /* Clear pending SysTick bit */
2545 #define SCB_ICSR_PENDSTSET ((u32)0x04000000) /* Set pending SysTick bit */
2546 #define SCB_ICSR_PENDSVCLR ((u32)0x08000000) /* Clear pending pendSV bit */
2547 #define SCB_ICSR_PENDSVSET ((u32)0x10000000) /* Set pending pendSV bit */
2548 #define SCB_ICSR_NMIPENDSET ((u32)0x80000000) /* Set pending NMI bit */
2549 
2550 
2551 /******************* Bit definition for SCB_VTOR register *******************/
2552 #define SCB_VTOR_TBLOFF ((u32)0x1FFFFF80) /* Vector table base offset field */
2553 #define SCB_VTOR_TBLBASE ((u32)0x20000000) /* Table base in code(0) or RAM(1) */
2554 
2555 
2556 /****************** Bit definition for SCB_AIRCR register *******************/
2557 #define SCB_AIRCR_VECTRESET ((u32)0x00000001) /* System Reset bit */
2558 #define SCB_AIRCR_VECTCLRACTIVE ((u32)0x00000002) /* Clear active vector bit */
2559 #define SCB_AIRCR_SYSRESETREQ ((u32)0x00000004) /* Requests chip control logic to generate a reset */
2560 
2561 #define SCB_AIRCR_PRIGROUP ((u32)0x00000700) /* PRIGROUP[2:0] bits (Priority group) */
2562 #define SCB_AIRCR_PRIGROUP_0 ((u32)0x00000100) /* Bit 0 */
2563 #define SCB_AIRCR_PRIGROUP_1 ((u32)0x00000200) /* Bit 1 */
2564 #define SCB_AIRCR_PRIGROUP_2 ((u32)0x00000400) /* Bit 2 */
2565 
2566 /* prority group configuration */
2567 #define SCB_AIRCR_PRIGROUP0 ((u32)0x00000000) /* Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
2568 #define SCB_AIRCR_PRIGROUP1 ((u32)0x00000100) /* Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
2569 #define SCB_AIRCR_PRIGROUP2 ((u32)0x00000200) /* Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
2570 #define SCB_AIRCR_PRIGROUP3 ((u32)0x00000300) /* Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
2571 #define SCB_AIRCR_PRIGROUP4 ((u32)0x00000400) /* Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
2572 #define SCB_AIRCR_PRIGROUP5 ((u32)0x00000500) /* Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
2573 #define SCB_AIRCR_PRIGROUP6 ((u32)0x00000600) /* Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
2574 #define SCB_AIRCR_PRIGROUP7 ((u32)0x00000700) /* Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
2575 
2576 #define SCB_AIRCR_ENDIANESS ((u32)0x00008000) /* Data endianness bit */
2577 #define SCB_AIRCR_VECTKEY ((u32)0xFFFF0000) /* Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
2578 
2579 
2580 /******************* Bit definition for SCB_SCR register ********************/
2581 #define SCB_SCR_SLEEPONEXIT ((u8)0x02) /* Sleep on exit bit */
2582 #define SCB_SCR_SLEEPDEEP ((u8)0x04) /* Sleep deep bit */
2583 #define SCB_SCR_SEVONPEND ((u8)0x10) /* Wake up from WFE */
2584 
2585 
2586 /******************** Bit definition for SCB_CCR register *******************/
2587 #define SCB_CCR_NONBASETHRDENA ((u16)0x0001) /* Thread mode can be entered from any level in Handler mode by controlled return value */
2588 #define SCB_CCR_USERSETMPEND ((u16)0x0002) /* Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
2589 #define SCB_CCR_UNALIGN_TRP ((u16)0x0008) /* Trap for unaligned access */
2590 #define SCB_CCR_DIV_0_TRP ((u16)0x0010) /* Trap on Divide by 0 */
2591 #define SCB_CCR_BFHFNMIGN ((u16)0x0100) /* Handlers running at priority -1 and -2 */
2592 #define SCB_CCR_STKALIGN ((u16)0x0200) /* On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
2593 
2594 
2595 /******************* Bit definition for SCB_SHPR register ********************/
2596 #define SCB_SHPR_PRI_N ((u32)0x000000FF) /* Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
2597 #define SCB_SHPR_PRI_N1 ((u32)0x0000FF00) /* Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
2598 #define SCB_SHPR_PRI_N2 ((u32)0x00FF0000) /* Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
2599 #define SCB_SHPR_PRI_N3 ((u32)0xFF000000) /* Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
2600 
2601 
2602 /****************** Bit definition for SCB_SHCSR register *******************/
2603 #define SCB_SHCSR_MEMFAULTACT ((u32)0x00000001) /* MemManage is active */
2604 #define SCB_SHCSR_BUSFAULTACT ((u32)0x00000002) /* BusFault is active */
2605 #define SCB_SHCSR_USGFAULTACT ((u32)0x00000008) /* UsageFault is active */
2606 #define SCB_SHCSR_SVCALLACT ((u32)0x00000080) /* SVCall is active */
2607 #define SCB_SHCSR_MONITORACT ((u32)0x00000100) /* Monitor is active */
2608 #define SCB_SHCSR_PENDSVACT ((u32)0x00000400) /* PendSV is active */
2609 #define SCB_SHCSR_SYSTICKACT ((u32)0x00000800) /* SysTick is active */
2610 #define SCB_SHCSR_USGFAULTPENDED ((u32)0x00001000) /* Usage Fault is pended */
2611 #define SCB_SHCSR_MEMFAULTPENDED ((u32)0x00002000) /* MemManage is pended */
2612 #define SCB_SHCSR_BUSFAULTPENDED ((u32)0x00004000) /* Bus Fault is pended */
2613 #define SCB_SHCSR_SVCALLPENDED ((u32)0x00008000) /* SVCall is pended */
2614 #define SCB_SHCSR_MEMFAULTENA ((u32)0x00010000) /* MemManage enable */
2615 #define SCB_SHCSR_BUSFAULTENA ((u32)0x00020000) /* Bus Fault enable */
2616 #define SCB_SHCSR_USGFAULTENA ((u32)0x00040000) /* UsageFault enable */
2617 
2618 
2619 /******************* Bit definition for SCB_CFSR register *******************/
2620 /* MFSR */
2621 #define SCB_CFSR_IACCVIOL ((u32)0x00000001) /* Instruction access violation */
2622 #define SCB_CFSR_DACCVIOL ((u32)0x00000002) /* Data access violation */
2623 #define SCB_CFSR_MUNSTKERR ((u32)0x00000008) /* Unstacking error */
2624 #define SCB_CFSR_MSTKERR ((u32)0x00000010) /* Stacking error */
2625 #define SCB_CFSR_MMARVALID ((u32)0x00000080) /* Memory Manage Address Register address valid flag */
2626 /* BFSR */
2627 #define SCB_CFSR_IBUSERR ((u32)0x00000100) /* Instruction bus error flag */
2628 #define SCB_CFSR_PRECISERR ((u32)0x00000200) /* Precise data bus error */
2629 #define SCB_CFSR_IMPRECISERR ((u32)0x00000400) /* Imprecise data bus error */
2630 #define SCB_CFSR_UNSTKERR ((u32)0x00000800) /* Unstacking error */
2631 #define SCB_CFSR_STKERR ((u32)0x00001000) /* Stacking error */
2632 #define SCB_CFSR_BFARVALID ((u32)0x00008000) /* Bus Fault Address Register address valid flag */
2633 /* UFSR */
2634 #define SCB_CFSR_UNDEFINSTR ((u32)0x00010000) /* The processor attempt to excecute an undefined instruction */
2635 #define SCB_CFSR_INVSTATE ((u32)0x00020000) /* Invalid combination of EPSR and instruction */
2636 #define SCB_CFSR_INVPC ((u32)0x00040000) /* Attempt to load EXC_RETURN into pc illegally */
2637 #define SCB_CFSR_NOCP ((u32)0x00080000) /* Attempt to use a coprocessor instruction */
2638 #define SCB_CFSR_UNALIGNED ((u32)0x01000000) /* Fault occurs when there is an attempt to make an unaligned memory access */
2639 #define SCB_CFSR_DIVBYZERO ((u32)0x02000000) /* Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
2640 
2641 
2642 /******************* Bit definition for SCB_HFSR register *******************/
2643 #define SCB_HFSR_VECTTBL ((u32)0x00000002) /* Fault occures because of vector table read on exception processing */
2644 #define SCB_HFSR_FORCED ((u32)0x40000000) /* Hard Fault activated when a configurable Fault was received and cannot activate */
2645 #define SCB_HFSR_DEBUGEVT ((u32)0x80000000) /* Fault related to debug */
2646 
2647 
2648 /******************* Bit definition for SCB_DFSR register *******************/
2649 #define SCB_DFSR_HALTED ((u8)0x01) /* Halt request flag */
2650 #define SCB_DFSR_BKPT ((u8)0x02) /* BKPT flag */
2651 #define SCB_DFSR_DWTTRAP ((u8)0x04) /* Data Watchpoint and Trace (DWT) flag */
2652 #define SCB_DFSR_VCATCH ((u8)0x08) /* Vector catch flag */
2653 #define SCB_DFSR_EXTERNAL ((u8)0x10) /* External debug request flag */
2654 
2655 
2656 /******************* Bit definition for SCB_MMFAR register ******************/
2657 #define SCB_MMFAR_ADDRESS ((u32)0xFFFFFFFF) /* Mem Manage fault address field */
2658 
2659 
2660 /******************* Bit definition for SCB_BFAR register *******************/
2661 #define SCB_BFAR_ADDRESS ((u32)0xFFFFFFFF) /* Bus fault address field */
2662 
2663 
2664 /******************* Bit definition for SCB_afsr register *******************/
2665 #define SCB_AFSR_IMPDEF ((u32)0xFFFFFFFF) /* Implementation defined */
2666 
2667 
2668 
2669 /******************************************************************************/
2670 /* */
2671 /* External Interrupt/Event Controller */
2672 /* */
2673 /******************************************************************************/
2674 
2675 /******************* Bit definition for EXTI_IMR register *******************/
2676 #define EXTI_IMR_MR0 ((u32)0x00000001) /* Interrupt Mask on line 0 */
2677 #define EXTI_IMR_MR1 ((u32)0x00000002) /* Interrupt Mask on line 1 */
2678 #define EXTI_IMR_MR2 ((u32)0x00000004) /* Interrupt Mask on line 2 */
2679 #define EXTI_IMR_MR3 ((u32)0x00000008) /* Interrupt Mask on line 3 */
2680 #define EXTI_IMR_MR4 ((u32)0x00000010) /* Interrupt Mask on line 4 */
2681 #define EXTI_IMR_MR5 ((u32)0x00000020) /* Interrupt Mask on line 5 */
2682 #define EXTI_IMR_MR6 ((u32)0x00000040) /* Interrupt Mask on line 6 */
2683 #define EXTI_IMR_MR7 ((u32)0x00000080) /* Interrupt Mask on line 7 */
2684 #define EXTI_IMR_MR8 ((u32)0x00000100) /* Interrupt Mask on line 8 */
2685 #define EXTI_IMR_MR9 ((u32)0x00000200) /* Interrupt Mask on line 9 */
2686 #define EXTI_IMR_MR10 ((u32)0x00000400) /* Interrupt Mask on line 10 */
2687 #define EXTI_IMR_MR11 ((u32)0x00000800) /* Interrupt Mask on line 11 */
2688 #define EXTI_IMR_MR12 ((u32)0x00001000) /* Interrupt Mask on line 12 */
2689 #define EXTI_IMR_MR13 ((u32)0x00002000) /* Interrupt Mask on line 13 */
2690 #define EXTI_IMR_MR14 ((u32)0x00004000) /* Interrupt Mask on line 14 */
2691 #define EXTI_IMR_MR15 ((u32)0x00008000) /* Interrupt Mask on line 15 */
2692 #define EXTI_IMR_MR16 ((u32)0x00010000) /* Interrupt Mask on line 16 */
2693 #define EXTI_IMR_MR17 ((u32)0x00020000) /* Interrupt Mask on line 17 */
2694 #define EXTI_IMR_MR18 ((u32)0x00040000) /* Interrupt Mask on line 18 */
2695 
2696 
2697 /******************* Bit definition for EXTI_EMR register *******************/
2698 #define EXTI_EMR_MR0 ((u32)0x00000001) /* Event Mask on line 0 */
2699 #define EXTI_EMR_MR1 ((u32)0x00000002) /* Event Mask on line 1 */
2700 #define EXTI_EMR_MR2 ((u32)0x00000004) /* Event Mask on line 2 */
2701 #define EXTI_EMR_MR3 ((u32)0x00000008) /* Event Mask on line 3 */
2702 #define EXTI_EMR_MR4 ((u32)0x00000010) /* Event Mask on line 4 */
2703 #define EXTI_EMR_MR5 ((u32)0x00000020) /* Event Mask on line 5 */
2704 #define EXTI_EMR_MR6 ((u32)0x00000040) /* Event Mask on line 6 */
2705 #define EXTI_EMR_MR7 ((u32)0x00000080) /* Event Mask on line 7 */
2706 #define EXTI_EMR_MR8 ((u32)0x00000100) /* Event Mask on line 8 */
2707 #define EXTI_EMR_MR9 ((u32)0x00000200) /* Event Mask on line 9 */
2708 #define EXTI_EMR_MR10 ((u32)0x00000400) /* Event Mask on line 10 */
2709 #define EXTI_EMR_MR11 ((u32)0x00000800) /* Event Mask on line 11 */
2710 #define EXTI_EMR_MR12 ((u32)0x00001000) /* Event Mask on line 12 */
2711 #define EXTI_EMR_MR13 ((u32)0x00002000) /* Event Mask on line 13 */
2712 #define EXTI_EMR_MR14 ((u32)0x00004000) /* Event Mask on line 14 */
2713 #define EXTI_EMR_MR15 ((u32)0x00008000) /* Event Mask on line 15 */
2714 #define EXTI_EMR_MR16 ((u32)0x00010000) /* Event Mask on line 16 */
2715 #define EXTI_EMR_MR17 ((u32)0x00020000) /* Event Mask on line 17 */
2716 #define EXTI_EMR_MR18 ((u32)0x00040000) /* Event Mask on line 18 */
2717 
2718 
2719 /****************** Bit definition for EXTI_RTSR register *******************/
2720 #define EXTI_RTSR_TR0 ((u32)0x00000001) /* Rising trigger event configuration bit of line 0 */
2721 #define EXTI_RTSR_TR1 ((u32)0x00000002) /* Rising trigger event configuration bit of line 1 */
2722 #define EXTI_RTSR_TR2 ((u32)0x00000004) /* Rising trigger event configuration bit of line 2 */
2723 #define EXTI_RTSR_TR3 ((u32)0x00000008) /* Rising trigger event configuration bit of line 3 */
2724 #define EXTI_RTSR_TR4 ((u32)0x00000010) /* Rising trigger event configuration bit of line 4 */
2725 #define EXTI_RTSR_TR5 ((u32)0x00000020) /* Rising trigger event configuration bit of line 5 */
2726 #define EXTI_RTSR_TR6 ((u32)0x00000040) /* Rising trigger event configuration bit of line 6 */
2727 #define EXTI_RTSR_TR7 ((u32)0x00000080) /* Rising trigger event configuration bit of line 7 */
2728 #define EXTI_RTSR_TR8 ((u32)0x00000100) /* Rising trigger event configuration bit of line 8 */
2729 #define EXTI_RTSR_TR9 ((u32)0x00000200) /* Rising trigger event configuration bit of line 9 */
2730 #define EXTI_RTSR_TR10 ((u32)0x00000400) /* Rising trigger event configuration bit of line 10 */
2731 #define EXTI_RTSR_TR11 ((u32)0x00000800) /* Rising trigger event configuration bit of line 11 */
2732 #define EXTI_RTSR_TR12 ((u32)0x00001000) /* Rising trigger event configuration bit of line 12 */
2733 #define EXTI_RTSR_TR13 ((u32)0x00002000) /* Rising trigger event configuration bit of line 13 */
2734 #define EXTI_RTSR_TR14 ((u32)0x00004000) /* Rising trigger event configuration bit of line 14 */
2735 #define EXTI_RTSR_TR15 ((u32)0x00008000) /* Rising trigger event configuration bit of line 15 */
2736 #define EXTI_RTSR_TR16 ((u32)0x00010000) /* Rising trigger event configuration bit of line 16 */
2737 #define EXTI_RTSR_TR17 ((u32)0x00020000) /* Rising trigger event configuration bit of line 17 */
2738 #define EXTI_RTSR_TR18 ((u32)0x00040000) /* Rising trigger event configuration bit of line 18 */
2739 
2740 
2741 /****************** Bit definition for EXTI_FTSR register *******************/
2742 #define EXTI_FTSR_TR0 ((u32)0x00000001) /* Falling trigger event configuration bit of line 0 */
2743 #define EXTI_FTSR_TR1 ((u32)0x00000002) /* Falling trigger event configuration bit of line 1 */
2744 #define EXTI_FTSR_TR2 ((u32)0x00000004) /* Falling trigger event configuration bit of line 2 */
2745 #define EXTI_FTSR_TR3 ((u32)0x00000008) /* Falling trigger event configuration bit of line 3 */
2746 #define EXTI_FTSR_TR4 ((u32)0x00000010) /* Falling trigger event configuration bit of line 4 */
2747 #define EXTI_FTSR_TR5 ((u32)0x00000020) /* Falling trigger event configuration bit of line 5 */
2748 #define EXTI_FTSR_TR6 ((u32)0x00000040) /* Falling trigger event configuration bit of line 6 */
2749 #define EXTI_FTSR_TR7 ((u32)0x00000080) /* Falling trigger event configuration bit of line 7 */
2750 #define EXTI_FTSR_TR8 ((u32)0x00000100) /* Falling trigger event configuration bit of line 8 */
2751 #define EXTI_FTSR_TR9 ((u32)0x00000200) /* Falling trigger event configuration bit of line 9 */
2752 #define EXTI_FTSR_TR10 ((u32)0x00000400) /* Falling trigger event configuration bit of line 10 */
2753 #define EXTI_FTSR_TR11 ((u32)0x00000800) /* Falling trigger event configuration bit of line 11 */
2754 #define EXTI_FTSR_TR12 ((u32)0x00001000) /* Falling trigger event configuration bit of line 12 */
2755 #define EXTI_FTSR_TR13 ((u32)0x00002000) /* Falling trigger event configuration bit of line 13 */
2756 #define EXTI_FTSR_TR14 ((u32)0x00004000) /* Falling trigger event configuration bit of line 14 */
2757 #define EXTI_FTSR_TR15 ((u32)0x00008000) /* Falling trigger event configuration bit of line 15 */
2758 #define EXTI_FTSR_TR16 ((u32)0x00010000) /* Falling trigger event configuration bit of line 16 */
2759 #define EXTI_FTSR_TR17 ((u32)0x00020000) /* Falling trigger event configuration bit of line 17 */
2760 #define EXTI_FTSR_TR18 ((u32)0x00040000) /* Falling trigger event configuration bit of line 18 */
2761 
2762 
2763 /****************** Bit definition for EXTI_SWIER register ******************/
2764 #define EXTI_SWIER_SWIER0 ((u32)0x00000001) /* Software Interrupt on line 0 */
2765 #define EXTI_SWIER_SWIER1 ((u32)0x00000002) /* Software Interrupt on line 1 */
2766 #define EXTI_SWIER_SWIER2 ((u32)0x00000004) /* Software Interrupt on line 2 */
2767 #define EXTI_SWIER_SWIER3 ((u32)0x00000008) /* Software Interrupt on line 3 */
2768 #define EXTI_SWIER_SWIER4 ((u32)0x00000010) /* Software Interrupt on line 4 */
2769 #define EXTI_SWIER_SWIER5 ((u32)0x00000020) /* Software Interrupt on line 5 */
2770 #define EXTI_SWIER_SWIER6 ((u32)0x00000040) /* Software Interrupt on line 6 */
2771 #define EXTI_SWIER_SWIER7 ((u32)0x00000080) /* Software Interrupt on line 7 */
2772 #define EXTI_SWIER_SWIER8 ((u32)0x00000100) /* Software Interrupt on line 8 */
2773 #define EXTI_SWIER_SWIER9 ((u32)0x00000200) /* Software Interrupt on line 9 */
2774 #define EXTI_SWIER_SWIER10 ((u32)0x00000400) /* Software Interrupt on line 10 */
2775 #define EXTI_SWIER_SWIER11 ((u32)0x00000800) /* Software Interrupt on line 11 */
2776 #define EXTI_SWIER_SWIER12 ((u32)0x00001000) /* Software Interrupt on line 12 */
2777 #define EXTI_SWIER_SWIER13 ((u32)0x00002000) /* Software Interrupt on line 13 */
2778 #define EXTI_SWIER_SWIER14 ((u32)0x00004000) /* Software Interrupt on line 14 */
2779 #define EXTI_SWIER_SWIER15 ((u32)0x00008000) /* Software Interrupt on line 15 */
2780 #define EXTI_SWIER_SWIER16 ((u32)0x00010000) /* Software Interrupt on line 16 */
2781 #define EXTI_SWIER_SWIER17 ((u32)0x00020000) /* Software Interrupt on line 17 */
2782 #define EXTI_SWIER_SWIER18 ((u32)0x00040000) /* Software Interrupt on line 18 */
2783 
2784 
2785 /******************* Bit definition for EXTI_PR register ********************/
2786 #define EXTI_PR_PR0 ((u32)0x00000001) /* Pending bit 0 */
2787 #define EXTI_PR_PR1 ((u32)0x00000002) /* Pending bit 1 */
2788 #define EXTI_PR_PR2 ((u32)0x00000004) /* Pending bit 2 */
2789 #define EXTI_PR_PR3 ((u32)0x00000008) /* Pending bit 3 */
2790 #define EXTI_PR_PR4 ((u32)0x00000010) /* Pending bit 4 */
2791 #define EXTI_PR_PR5 ((u32)0x00000020) /* Pending bit 5 */
2792 #define EXTI_PR_PR6 ((u32)0x00000040) /* Pending bit 6 */
2793 #define EXTI_PR_PR7 ((u32)0x00000080) /* Pending bit 7 */
2794 #define EXTI_PR_PR8 ((u32)0x00000100) /* Pending bit 8 */
2795 #define EXTI_PR_PR9 ((u32)0x00000200) /* Pending bit 9 */
2796 #define EXTI_PR_PR10 ((u32)0x00000400) /* Pending bit 10 */
2797 #define EXTI_PR_PR11 ((u32)0x00000800) /* Pending bit 11 */
2798 #define EXTI_PR_PR12 ((u32)0x00001000) /* Pending bit 12 */
2799 #define EXTI_PR_PR13 ((u32)0x00002000) /* Pending bit 13 */
2800 #define EXTI_PR_PR14 ((u32)0x00004000) /* Pending bit 14 */
2801 #define EXTI_PR_PR15 ((u32)0x00008000) /* Pending bit 15 */
2802 #define EXTI_PR_PR16 ((u32)0x00010000) /* Pending bit 16 */
2803 #define EXTI_PR_PR17 ((u32)0x00020000) /* Pending bit 17 */
2804 #define EXTI_PR_PR18 ((u32)0x00040000) /* Trigger request occurred on the external interrupt line 18 */
2805 
2806 
2807 
2808 /******************************************************************************/
2809 /* */
2810 /* DMA Controller */
2811 /* */
2812 /******************************************************************************/
2813 
2814 /******************* Bit definition for DMA_ISR register ********************/
2815 #define DMA_ISR_GIF1 ((u32)0x00000001) /* Channel 1 Global interrupt flag */
2816 #define DMA_ISR_TCIF1 ((u32)0x00000002) /* Channel 1 Transfer Complete flag */
2817 #define DMA_ISR_HTIF1 ((u32)0x00000004) /* Channel 1 Half Transfer flag */
2818 #define DMA_ISR_TEIF1 ((u32)0x00000008) /* Channel 1 Transfer Error flag */
2819 #define DMA_ISR_GIF2 ((u32)0x00000010) /* Channel 2 Global interrupt flag */
2820 #define DMA_ISR_TCIF2 ((u32)0x00000020) /* Channel 2 Transfer Complete flag */
2821 #define DMA_ISR_HTIF2 ((u32)0x00000040) /* Channel 2 Half Transfer flag */
2822 #define DMA_ISR_TEIF2 ((u32)0x00000080) /* Channel 2 Transfer Error flag */
2823 #define DMA_ISR_GIF3 ((u32)0x00000100) /* Channel 3 Global interrupt flag */
2824 #define DMA_ISR_TCIF3 ((u32)0x00000200) /* Channel 3 Transfer Complete flag */
2825 #define DMA_ISR_HTIF3 ((u32)0x00000400) /* Channel 3 Half Transfer flag */
2826 #define DMA_ISR_TEIF3 ((u32)0x00000800) /* Channel 3 Transfer Error flag */
2827 #define DMA_ISR_GIF4 ((u32)0x00001000) /* Channel 4 Global interrupt flag */
2828 #define DMA_ISR_TCIF4 ((u32)0x00002000) /* Channel 4 Transfer Complete flag */
2829 #define DMA_ISR_HTIF4 ((u32)0x00004000) /* Channel 4 Half Transfer flag */
2830 #define DMA_ISR_TEIF4 ((u32)0x00008000) /* Channel 4 Transfer Error flag */
2831 #define DMA_ISR_GIF5 ((u32)0x00010000) /* Channel 5 Global interrupt flag */
2832 #define DMA_ISR_TCIF5 ((u32)0x00020000) /* Channel 5 Transfer Complete flag */
2833 #define DMA_ISR_HTIF5 ((u32)0x00040000) /* Channel 5 Half Transfer flag */
2834 #define DMA_ISR_TEIF5 ((u32)0x00080000) /* Channel 5 Transfer Error flag */
2835 #define DMA_ISR_GIF6 ((u32)0x00100000) /* Channel 6 Global interrupt flag */
2836 #define DMA_ISR_TCIF6 ((u32)0x00200000) /* Channel 6 Transfer Complete flag */
2837 #define DMA_ISR_HTIF6 ((u32)0x00400000) /* Channel 6 Half Transfer flag */
2838 #define DMA_ISR_TEIF6 ((u32)0x00800000) /* Channel 6 Transfer Error flag */
2839 #define DMA_ISR_GIF7 ((u32)0x01000000) /* Channel 7 Global interrupt flag */
2840 #define DMA_ISR_TCIF7 ((u32)0x02000000) /* Channel 7 Transfer Complete flag */
2841 #define DMA_ISR_HTIF7 ((u32)0x04000000) /* Channel 7 Half Transfer flag */
2842 #define DMA_ISR_TEIF7 ((u32)0x08000000) /* Channel 7 Transfer Error flag */
2843 
2844 
2845 /******************* Bit definition for DMA_IFCR register *******************/
2846 #define DMA_IFCR_CGIF1 ((u32)0x00000001) /* Channel 1 Global interrupt clearr */
2847 #define DMA_IFCR_CTCIF1 ((u32)0x00000002) /* Channel 1 Transfer Complete clear */
2848 #define DMA_IFCR_CHTIF1 ((u32)0x00000004) /* Channel 1 Half Transfer clear */
2849 #define DMA_IFCR_CTEIF1 ((u32)0x00000008) /* Channel 1 Transfer Error clear */
2850 #define DMA_IFCR_CGIF2 ((u32)0x00000010) /* Channel 2 Global interrupt clear */
2851 #define DMA_IFCR_CTCIF2 ((u32)0x00000020) /* Channel 2 Transfer Complete clear */
2852 #define DMA_IFCR_CHTIF2 ((u32)0x00000040) /* Channel 2 Half Transfer clear */
2853 #define DMA_IFCR_CTEIF2 ((u32)0x00000080) /* Channel 2 Transfer Error clear */
2854 #define DMA_IFCR_CGIF3 ((u32)0x00000100) /* Channel 3 Global interrupt clear */
2855 #define DMA_IFCR_CTCIF3 ((u32)0x00000200) /* Channel 3 Transfer Complete clear */
2856 #define DMA_IFCR_CHTIF3 ((u32)0x00000400) /* Channel 3 Half Transfer clear */
2857 #define DMA_IFCR_CTEIF3 ((u32)0x00000800) /* Channel 3 Transfer Error clear */
2858 #define DMA_IFCR_CGIF4 ((u32)0x00001000) /* Channel 4 Global interrupt clear */
2859 #define DMA_IFCR_CTCIF4 ((u32)0x00002000) /* Channel 4 Transfer Complete clear */
2860 #define DMA_IFCR_CHTIF4 ((u32)0x00004000) /* Channel 4 Half Transfer clear */
2861 #define DMA_IFCR_CTEIF4 ((u32)0x00008000) /* Channel 4 Transfer Error clear */
2862 #define DMA_IFCR_CGIF5 ((u32)0x00010000) /* Channel 5 Global interrupt clear */
2863 #define DMA_IFCR_CTCIF5 ((u32)0x00020000) /* Channel 5 Transfer Complete clear */
2864 #define DMA_IFCR_CHTIF5 ((u32)0x00040000) /* Channel 5 Half Transfer clear */
2865 #define DMA_IFCR_CTEIF5 ((u32)0x00080000) /* Channel 5 Transfer Error clear */
2866 #define DMA_IFCR_CGIF6 ((u32)0x00100000) /* Channel 6 Global interrupt clear */
2867 #define DMA_IFCR_CTCIF6 ((u32)0x00200000) /* Channel 6 Transfer Complete clear */
2868 #define DMA_IFCR_CHTIF6 ((u32)0x00400000) /* Channel 6 Half Transfer clear */
2869 #define DMA_IFCR_CTEIF6 ((u32)0x00800000) /* Channel 6 Transfer Error clear */
2870 #define DMA_IFCR_CGIF7 ((u32)0x01000000) /* Channel 7 Global interrupt clear */
2871 #define DMA_IFCR_CTCIF7 ((u32)0x02000000) /* Channel 7 Transfer Complete clear */
2872 #define DMA_IFCR_CHTIF7 ((u32)0x04000000) /* Channel 7 Half Transfer clear */
2873 #define DMA_IFCR_CTEIF7 ((u32)0x08000000) /* Channel 7 Transfer Error clear */
2874 
2875 
2876 /******************* Bit definition for DMA_CCR1 register *******************/
2877 #define DMA_CCR1_EN ((u16)0x0001) /* Channel enable*/
2878 #define DMA_CCR1_TCIE ((u16)0x0002) /* Transfer complete interrupt enable */
2879 #define DMA_CCR1_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */
2880 #define DMA_CCR1_TEIE ((u16)0x0008) /* Transfer error interrupt enable */
2881 #define DMA_CCR1_DIR ((u16)0x0010) /* Data transfer direction */
2882 #define DMA_CCR1_CIRC ((u16)0x0020) /* Circular mode */
2883 #define DMA_CCR1_PINC ((u16)0x0040) /* Peripheral increment mode */
2884 #define DMA_CCR1_MINC ((u16)0x0080) /* Memory increment mode */
2885 
2886 #define DMA_CCR1_PSIZE ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
2887 #define DMA_CCR1_PSIZE_0 ((u16)0x0100) /* Bit 0 */
2888 #define DMA_CCR1_PSIZE_1 ((u16)0x0200) /* Bit 1 */
2889 
2890 #define DMA_CCR1_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */
2891 #define DMA_CCR1_MSIZE_0 ((u16)0x0400) /* Bit 0 */
2892 #define DMA_CCR1_MSIZE_1 ((u16)0x0800) /* Bit 1 */
2893 
2894 #define DMA_CCR1_PL ((u16)0x3000) /* PL[1:0] bits(Channel Priority level) */
2895 #define DMA_CCR1_PL_0 ((u16)0x1000) /* Bit 0 */
2896 #define DMA_CCR1_PL_1 ((u16)0x2000) /* Bit 1 */
2897 
2898 #define DMA_CCR1_MEM2MEM ((u16)0x4000) /* Memory to memory mode */
2899 
2900 
2901 /******************* Bit definition for DMA_CCR2 register *******************/
2902 #define DMA_CCR2_EN ((u16)0x0001) /* Channel enable */
2903 #define DMA_CCR2_TCIE ((u16)0x0002) /* ransfer complete interrupt enable */
2904 #define DMA_CCR2_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */
2905 #define DMA_CCR2_TEIE ((u16)0x0008) /* Transfer error interrupt enable */
2906 #define DMA_CCR2_DIR ((u16)0x0010) /* Data transfer direction */
2907 #define DMA_CCR2_CIRC ((u16)0x0020) /* Circular mode */
2908 #define DMA_CCR2_PINC ((u16)0x0040) /* Peripheral increment mode */
2909 #define DMA_CCR2_MINC ((u16)0x0080) /* Memory increment mode */
2910 
2911 #define DMA_CCR2_PSIZE ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
2912 #define DMA_CCR2_PSIZE_0 ((u16)0x0100) /* Bit 0 */
2913 #define DMA_CCR2_PSIZE_1 ((u16)0x0200) /* Bit 1 */
2914 
2915 #define DMA_CCR2_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */
2916 #define DMA_CCR2_MSIZE_0 ((u16)0x0400) /* Bit 0 */
2917 #define DMA_CCR2_MSIZE_1 ((u16)0x0800) /* Bit 1 */
2918 
2919 #define DMA_CCR2_PL ((u16)0x3000) /* PL[1:0] bits (Channel Priority level) */
2920 #define DMA_CCR2_PL_0 ((u16)0x1000) /* Bit 0 */
2921 #define DMA_CCR2_PL_1 ((u16)0x2000) /* Bit 1 */
2922 
2923 #define DMA_CCR2_MEM2MEM ((u16)0x4000) /* Memory to memory mode */
2924 
2925 
2926 /******************* Bit definition for DMA_CCR3 register *******************/
2927 #define DMA_CCR3_EN ((u16)0x0001) /* Channel enable */
2928 #define DMA_CCR3_TCIE ((u16)0x0002) /* Transfer complete interrupt enable */
2929 #define DMA_CCR3_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */
2930 #define DMA_CCR3_TEIE ((u16)0x0008) /* Transfer error interrupt enable */
2931 #define DMA_CCR3_DIR ((u16)0x0010) /* Data transfer direction */
2932 #define DMA_CCR3_CIRC ((u16)0x0020) /* Circular mode */
2933 #define DMA_CCR3_PINC ((u16)0x0040) /* Peripheral increment mode */
2934 #define DMA_CCR3_MINC ((u16)0x0080) /* Memory increment mode */
2935 
2936 #define DMA_CCR3_PSIZE ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
2937 #define DMA_CCR3_PSIZE_0 ((u16)0x0100) /* Bit 0 */
2938 #define DMA_CCR3_PSIZE_1 ((u16)0x0200) /* Bit 1 */
2939 
2940 #define DMA_CCR3_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */
2941 #define DMA_CCR3_MSIZE_0 ((u16)0x0400) /* Bit 0 */
2942 #define DMA_CCR3_MSIZE_1 ((u16)0x0800) /* Bit 1 */
2943 
2944 #define DMA_CCR3_PL ((u16)0x3000) /* PL[1:0] bits (Channel Priority level) */
2945 #define DMA_CCR3_PL_0 ((u16)0x1000) /* Bit 0 */
2946 #define DMA_CCR3_PL_1 ((u16)0x2000) /* Bit 1 */
2947 
2948 #define DMA_CCR3_MEM2MEM ((u16)0x4000) /* Memory to memory mode */
2949 
2950 
2951 /******************* Bit definition for DMA_CCR4 register *******************/
2952 #define DMA_CCR4_EN ((u16)0x0001) /* Channel enable */
2953 #define DMA_CCR4_TCIE ((u16)0x0002) /* Transfer complete interrupt enable */
2954 #define DMA_CCR4_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */
2955 #define DMA_CCR4_TEIE ((u16)0x0008) /* Transfer error interrupt enable */
2956 #define DMA_CCR4_DIR ((u16)0x0010) /* Data transfer direction */
2957 #define DMA_CCR4_CIRC ((u16)0x0020) /* Circular mode */
2958 #define DMA_CCR4_PINC ((u16)0x0040) /* Peripheral increment mode */
2959 #define DMA_CCR4_MINC ((u16)0x0080) /* Memory increment mode */
2960 
2961 #define DMA_CCR4_PSIZE ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
2962 #define DMA_CCR4_PSIZE_0 ((u16)0x0100) /* Bit 0 */
2963 #define DMA_CCR4_PSIZE_1 ((u16)0x0200) /* Bit 1 */
2964 
2965 #define DMA_CCR4_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */
2966 #define DMA_CCR4_MSIZE_0 ((u16)0x0400) /* Bit 0 */
2967 #define DMA_CCR4_MSIZE_1 ((u16)0x0800) /* Bit 1 */
2968 
2969 #define DMA_CCR4_PL ((u16)0x3000) /* PL[1:0] bits (Channel Priority level) */
2970 #define DMA_CCR4_PL_0 ((u16)0x1000) /* Bit 0 */
2971 #define DMA_CCR4_PL_1 ((u16)0x2000) /* Bit 1 */
2972 
2973 #define DMA_CCR4_MEM2MEM ((u16)0x4000) /* Memory to memory mode */
2974 
2975 
2976 /****************** Bit definition for DMA_CCR5 register *******************/
2977 #define DMA_CCR5_EN ((u16)0x0001) /* Channel enable */
2978 #define DMA_CCR5_TCIE ((u16)0x0002) /* Transfer complete interrupt enable */
2979 #define DMA_CCR5_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */
2980 #define DMA_CCR5_TEIE ((u16)0x0008) /* Transfer error interrupt enable */
2981 #define DMA_CCR5_DIR ((u16)0x0010) /* Data transfer direction */
2982 #define DMA_CCR5_CIRC ((u16)0x0020) /* Circular mode */
2983 #define DMA_CCR5_PINC ((u16)0x0040) /* Peripheral increment mode */
2984 #define DMA_CCR5_MINC ((u16)0x0080) /* Memory increment mode */
2985 
2986 #define DMA_CCR5_PSIZE ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
2987 #define DMA_CCR5_PSIZE_0 ((u16)0x0100) /* Bit 0 */
2988 #define DMA_CCR5_PSIZE_1 ((u16)0x0200) /* Bit 1 */
2989 
2990 #define DMA_CCR5_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */
2991 #define DMA_CCR5_MSIZE_0 ((u16)0x0400) /* Bit 0 */
2992 #define DMA_CCR5_MSIZE_1 ((u16)0x0800) /* Bit 1 */
2993 
2994 #define DMA_CCR5_PL ((u16)0x3000) /* PL[1:0] bits (Channel Priority level) */
2995 #define DMA_CCR5_PL_0 ((u16)0x1000) /* Bit 0 */
2996 #define DMA_CCR5_PL_1 ((u16)0x2000) /* Bit 1 */
2997 
2998 #define DMA_CCR5_MEM2MEM ((u16)0x4000) /* Memory to memory mode enable */
2999 
3000 
3001 /******************* Bit definition for DMA_CCR6 register *******************/
3002 #define DMA_CCR6_EN ((u16)0x0001) /* Channel enable */
3003 #define DMA_CCR6_TCIE ((u16)0x0002) /* Transfer complete interrupt enable */
3004 #define DMA_CCR6_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */
3005 #define DMA_CCR6_TEIE ((u16)0x0008) /* Transfer error interrupt enable */
3006 #define DMA_CCR6_DIR ((u16)0x0010) /* Data transfer direction */
3007 #define DMA_CCR6_CIRC ((u16)0x0020) /* Circular mode */
3008 #define DMA_CCR6_PINC ((u16)0x0040) /* Peripheral increment mode */
3009 #define DMA_CCR6_MINC ((u16)0x0080) /* Memory increment mode */
3010 
3011 #define DMA_CCR6_PSIZE ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
3012 #define DMA_CCR6_PSIZE_0 ((u16)0x0100) /* Bit 0 */
3013 #define DMA_CCR6_PSIZE_1 ((u16)0x0200) /* Bit 1 */
3014 
3015 #define DMA_CCR6_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */
3016 #define DMA_CCR6_MSIZE_0 ((u16)0x0400) /* Bit 0 */
3017 #define DMA_CCR6_MSIZE_1 ((u16)0x0800) /* Bit 1 */
3018 
3019 #define DMA_CCR6_PL ((u16)0x3000) /* PL[1:0] bits (Channel Priority level) */
3020 #define DMA_CCR6_PL_0 ((u16)0x1000) /* Bit 0 */
3021 #define DMA_CCR6_PL_1 ((u16)0x2000) /* Bit 1 */
3022 
3023 #define DMA_CCR6_MEM2MEM ((u16)0x4000) /* Memory to memory mode */
3024 
3025 
3026 /******************* Bit definition for DMA_CCR7 register *******************/
3027 #define DMA_CCR7_EN ((u16)0x0001) /* Channel enable */
3028 #define DMA_CCR7_TCIE ((u16)0x0002) /* Transfer complete interrupt enable */
3029 #define DMA_CCR7_HTIE ((u16)0x0004) /* Half Transfer interrupt enable */
3030 #define DMA_CCR7_TEIE ((u16)0x0008) /* Transfer error interrupt enable */
3031 #define DMA_CCR7_DIR ((u16)0x0010) /* Data transfer direction */
3032 #define DMA_CCR7_CIRC ((u16)0x0020) /* Circular mode */
3033 #define DMA_CCR7_PINC ((u16)0x0040) /* Peripheral increment mode */
3034 #define DMA_CCR7_MINC ((u16)0x0080) /* Memory increment mode */
3035 
3036 #define DMA_CCR7_PSIZE , ((u16)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
3037 #define DMA_CCR7_PSIZE_0 ((u16)0x0100) /* Bit 0 */
3038 #define DMA_CCR7_PSIZE_1 ((u16)0x0200) /* Bit 1 */
3039 
3040 #define DMA_CCR7_MSIZE ((u16)0x0C00) /* MSIZE[1:0] bits (Memory size) */
3041 #define DMA_CCR7_MSIZE_0 ((u16)0x0400) /* Bit 0 */
3042 #define DMA_CCR7_MSIZE_1 ((u16)0x0800) /* Bit 1 */
3043 
3044 #define DMA_CCR7_PL ((u16)0x3000) /* PL[1:0] bits (Channel Priority level) */
3045 #define DMA_CCR7_PL_0 ((u16)0x1000) /* Bit 0 */
3046 #define DMA_CCR7_PL_1 ((u16)0x2000) /* Bit 1 */
3047 
3048 #define DMA_CCR7_MEM2MEM ((u16)0x4000) /* Memory to memory mode enable */
3049 
3050 
3051 /****************** Bit definition for DMA_CNDTR1 register ******************/
3052 #define DMA_CNDTR1_NDT ((u16)0xFFFF) /* Number of data to Transfer */
3053 
3054 
3055 /****************** Bit definition for DMA_CNDTR2 register ******************/
3056 #define DMA_CNDTR2_NDT ((u16)0xFFFF) /* Number of data to Transfer */
3057 
3058 
3059 /****************** Bit definition for DMA_CNDTR3 register ******************/
3060 #define DMA_CNDTR3_NDT ((u16)0xFFFF) /* Number of data to Transfer */
3061 
3062 
3063 /****************** Bit definition for DMA_CNDTR4 register ******************/
3064 #define DMA_CNDTR4_NDT ((u16)0xFFFF) /* Number of data to Transfer */
3065 
3066 
3067 /****************** Bit definition for DMA_CNDTR5 register ******************/
3068 #define DMA_CNDTR5_NDT ((u16)0xFFFF) /* Number of data to Transfer */
3069 
3070 
3071 /****************** Bit definition for DMA_CNDTR6 register ******************/
3072 #define DMA_CNDTR6_NDT ((u16)0xFFFF) /* Number of data to Transfer */
3073 
3074 
3075 /****************** Bit definition for DMA_CNDTR7 register ******************/
3076 #define DMA_CNDTR7_NDT ((u16)0xFFFF) /* Number of data to Transfer */
3077 
3078 
3079 /****************** Bit definition for DMA_CPAR1 register *******************/
3080 #define DMA_CPAR1_PA ((u32)0xFFFFFFFF) /* Peripheral Address */
3081 
3082 
3083 /****************** Bit definition for DMA_CPAR2 register *******************/
3084 #define DMA_CPAR2_PA ((u32)0xFFFFFFFF) /* Peripheral Address */
3085 
3086 
3087 /****************** Bit definition for DMA_CPAR3 register *******************/
3088 #define DMA_CPAR3_PA ((u32)0xFFFFFFFF) /* Peripheral Address */
3089 
3090 
3091 /****************** Bit definition for DMA_CPAR4 register *******************/
3092 #define DMA_CPAR4_PA ((u32)0xFFFFFFFF) /* Peripheral Address */
3093 
3094 
3095 /****************** Bit definition for DMA_CPAR5 register *******************/
3096 #define DMA_CPAR5_PA ((u32)0xFFFFFFFF) /* Peripheral Address */
3097 
3098 
3099 /****************** Bit definition for DMA_CPAR6 register *******************/
3100 #define DMA_CPAR6_PA ((u32)0xFFFFFFFF) /* Peripheral Address */
3101 
3102 
3103 /****************** Bit definition for DMA_CPAR7 register *******************/
3104 #define DMA_CPAR7_PA ((u32)0xFFFFFFFF) /* Peripheral Address */
3105 
3106 
3107 /****************** Bit definition for DMA_CMAR1 register *******************/
3108 #define DMA_CMAR1_MA ((u32)0xFFFFFFFF) /* Memory Address */
3109 
3110 
3111 /****************** Bit definition for DMA_CMAR2 register *******************/
3112 #define DMA_CMAR2_MA ((u32)0xFFFFFFFF) /* Memory Address */
3113 
3114 
3115 /****************** Bit definition for DMA_CMAR3 register *******************/
3116 #define DMA_CMAR3_MA ((u32)0xFFFFFFFF) /* Memory Address */
3117 
3118 
3119 /****************** Bit definition for DMA_CMAR4 register *******************/
3120 #define DMA_CMAR4_MA ((u32)0xFFFFFFFF) /* Memory Address */
3121 
3122 
3123 /****************** Bit definition for DMA_CMAR5 register *******************/
3124 #define DMA_CMAR5_MA ((u32)0xFFFFFFFF) /* Memory Address */
3125 
3126 
3127 /****************** Bit definition for DMA_CMAR6 register *******************/
3128 #define DMA_CMAR6_MA ((u32)0xFFFFFFFF) /* Memory Address */
3129 
3130 
3131 /****************** Bit definition for DMA_CMAR7 register *******************/
3132 #define DMA_CMAR7_MA ((u32)0xFFFFFFFF) /* Memory Address */
3133 
3134 
3135 
3136 /******************************************************************************/
3137 /* */
3138 /* Analog to Digital Converter */
3139 /* */
3140 /******************************************************************************/
3141 
3142 /******************** Bit definition for ADC_SR register ********************/
3143 #define ADC_SR_AWD ((u8)0x01) /* Analog watchdog flag */
3144 #define ADC_SR_EOC ((u8)0x02) /* End of conversion */
3145 #define ADC_SR_JEOC ((u8)0x04) /* Injected channel end of conversion */
3146 #define ADC_SR_JSTRT ((u8)0x08) /* Injected channel Start flag */
3147 #define ADC_SR_STRT ((u8)0x10) /* Regular channel Start flag */
3148 
3149 
3150 /******************* Bit definition for ADC_CR1 register ********************/
3151 #define ADC_CR1_AWDCH ((u32)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */
3152 #define ADC_CR1_AWDCH_0 ((u32)0x00000001) /* Bit 0 */
3153 #define ADC_CR1_AWDCH_1 ((u32)0x00000002) /* Bit 1 */
3154 #define ADC_CR1_AWDCH_2 ((u32)0x00000004) /* Bit 2 */
3155 #define ADC_CR1_AWDCH_3 ((u32)0x00000008) /* Bit 3 */
3156 #define ADC_CR1_AWDCH_4 ((u32)0x00000010) /* Bit 4 */
3157 
3158 #define ADC_CR1_EOCIE ((u32)0x00000020) /* Interrupt enable for EOC */
3159 #define ADC_CR1_AWDIE ((u32)0x00000040) /* AAnalog Watchdog interrupt enable */
3160 #define ADC_CR1_JEOCIE ((u32)0x00000080) /* Interrupt enable for injected channels */
3161 #define ADC_CR1_SCAN ((u32)0x00000100) /* Scan mode */
3162 #define ADC_CR1_AWDSGL ((u32)0x00000200) /* Enable the watchdog on a single channel in scan mode */
3163 #define ADC_CR1_JAUTO ((u32)0x00000400) /* Automatic injected group conversion */
3164 #define ADC_CR1_DISCEN ((u32)0x00000800) /* Discontinuous mode on regular channels */
3165 #define ADC_CR1_JDISCEN ((u32)0x00001000) /* Discontinuous mode on injected channels */
3166 
3167 #define ADC_CR1_DISCNUM ((u32)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */
3168 #define ADC_CR1_DISCNUM_0 ((u32)0x00002000) /* Bit 0 */
3169 #define ADC_CR1_DISCNUM_1 ((u32)0x00004000) /* Bit 1 */
3170 #define ADC_CR1_DISCNUM_2 ((u32)0x00008000) /* Bit 2 */
3171 
3172 #define ADC_CR1_DUALMOD ((u32)0x000F0000) /* DUALMOD[3:0] bits (Dual mode selection) */
3173 #define ADC_CR1_DUALMOD_0 ((u32)0x00010000) /* Bit 0 */
3174 #define ADC_CR1_DUALMOD_1 ((u32)0x00020000) /* Bit 1 */
3175 #define ADC_CR1_DUALMOD_2 ((u32)0x00040000) /* Bit 2 */
3176 #define ADC_CR1_DUALMOD_3 ((u32)0x00080000) /* Bit 3 */
3177 
3178 #define ADC_CR1_JAWDEN ((u32)0x00400000) /* Analog watchdog enable on injected channels */
3179 #define ADC_CR1_AWDEN ((u32)0x00800000) /* Analog watchdog enable on regular channels */
3180 
3181 
3182 /******************* Bit definition for ADC_CR2 register ********************/
3183 #define ADC_CR2_ADON ((u32)0x00000001) /* A/D Converter ON / OFF */
3184 #define ADC_CR2_CONT ((u32)0x00000002) /* Continuous Conversion */
3185 #define ADC_CR2_CAL ((u32)0x00000004) /* A/D Calibration */
3186 #define ADC_CR2_RSTCAL ((u32)0x00000008) /* Reset Calibration */
3187 #define ADC_CR2_DMA ((u32)0x00000100) /* Direct Memory access mode */
3188 #define ADC_CR2_ALIGN ((u32)0x00000800) /* Data Alignment */
3189 
3190 #define ADC_CR2_JEXTSEL ((u32)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */
3191 #define ADC_CR2_JEXTSEL_0 ((u32)0x00001000) /* Bit 0 */
3192 #define ADC_CR2_JEXTSEL_1 ((u32)0x00002000) /* Bit 1 */
3193 #define ADC_CR2_JEXTSEL_2 ((u32)0x00004000) /* Bit 2 */
3194 
3195 #define ADC_CR2_JEXTTRIG ((u32)0x00008000) /* External Trigger Conversion mode for injected channels */
3196 
3197 #define ADC_CR2_EXTSEL ((u32)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */
3198 #define ADC_CR2_EXTSEL_0 ((u32)0x00020000) /* Bit 0 */
3199 #define ADC_CR2_EXTSEL_1 ((u32)0x00040000) /* Bit 1 */
3200 #define ADC_CR2_EXTSEL_2 ((u32)0x00080000) /* Bit 2 */
3201 
3202 #define ADC_CR2_EXTTRIG ((u32)0x00100000) /* External Trigger Conversion mode for regular channels */
3203 #define ADC_CR2_JSWSTART ((u32)0x00200000) /* Start Conversion of injected channels */
3204 #define ADC_CR2_SWSTART ((u32)0x00400000) /* Start Conversion of regular channels */
3205 #define ADC_CR2_TSVREFE ((u32)0x00800000) /* Temperature Sensor and VREFINT Enable */
3206 
3207 
3208 /****************** Bit definition for ADC_SMPR1 register *******************/
3209 #define ADC_SMPR1_SMP10 ((u32)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */
3210 #define ADC_SMPR1_SMP10_0 ((u32)0x00000001) /* Bit 0 */
3211 #define ADC_SMPR1_SMP10_1 ((u32)0x00000002) /* Bit 1 */
3212 #define ADC_SMPR1_SMP10_2 ((u32)0x00000004) /* Bit 2 */
3213 
3214 #define ADC_SMPR1_SMP11 ((u32)0x00000038) /* SMP11[2:0] bits (Channel 11 Sample time selection) */
3215 #define ADC_SMPR1_SMP11_0 ((u32)0x00000008) /* Bit 0 */
3216 #define ADC_SMPR1_SMP11_1 ((u32)0x00000010) /* Bit 1 */
3217 #define ADC_SMPR1_SMP11_2 ((u32)0x00000020) /* Bit 2 */
3218 
3219 #define ADC_SMPR1_SMP12 ((u32)0x000001C0) /* SMP12[2:0] bits (Channel 12 Sample time selection) */
3220 #define ADC_SMPR1_SMP12_0 ((u32)0x00000040) /* Bit 0 */
3221 #define ADC_SMPR1_SMP12_1 ((u32)0x00000080) /* Bit 1 */
3222 #define ADC_SMPR1_SMP12_2 ((u32)0x00000100) /* Bit 2 */
3223 
3224 #define ADC_SMPR1_SMP13 ((u32)0x00000E00) /* SMP13[2:0] bits (Channel 13 Sample time selection) */
3225 #define ADC_SMPR1_SMP13_0 ((u32)0x00000200) /* Bit 0 */
3226 #define ADC_SMPR1_SMP13_1 ((u32)0x00000400) /* Bit 1 */
3227 #define ADC_SMPR1_SMP13_2 ((u32)0x00000800) /* Bit 2 */
3228 
3229 #define ADC_SMPR1_SMP14 ((u32)0x00007000) /* SMP14[2:0] bits (Channel 14 Sample time selection) */
3230 #define ADC_SMPR1_SMP14_0 ((u32)0x00001000) /* Bit 0 */
3231 #define ADC_SMPR1_SMP14_1 ((u32)0x00002000) /* Bit 1 */
3232 #define ADC_SMPR1_SMP14_2 ((u32)0x00004000) /* Bit 2 */
3233 
3234 #define ADC_SMPR1_SMP15 ((u32)0x00038000) /* SMP15[2:0] bits (Channel 15 Sample time selection) */
3235 #define ADC_SMPR1_SMP15_0 ((u32)0x00008000) /* Bit 0 */
3236 #define ADC_SMPR1_SMP15_1 ((u32)0x00010000) /* Bit 1 */
3237 #define ADC_SMPR1_SMP15_2 ((u32)0x00020000) /* Bit 2 */
3238 
3239 #define ADC_SMPR1_SMP16 ((u32)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */
3240 #define ADC_SMPR1_SMP16_0 ((u32)0x00040000) /* Bit 0 */
3241 #define ADC_SMPR1_SMP16_1 ((u32)0x00080000) /* Bit 1 */
3242 #define ADC_SMPR1_SMP16_2 ((u32)0x00100000) /* Bit 2 */
3243 
3244 #define ADC_SMPR1_SMP17 ((u32)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */
3245 #define ADC_SMPR1_SMP17_0 ((u32)0x00200000) /* Bit 0 */
3246 #define ADC_SMPR1_SMP17_1 ((u32)0x00400000) /* Bit 1 */
3247 #define ADC_SMPR1_SMP17_2 ((u32)0x00800000) /* Bit 2 */
3248 
3249 
3250 /****************** Bit definition for ADC_SMPR2 register *******************/
3251 #define ADC_SMPR2_SMP0 ((u32)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */
3252 #define ADC_SMPR2_SMP0_0 ((u32)0x00000001) /* Bit 0 */
3253 #define ADC_SMPR2_SMP0_1 ((u32)0x00000002) /* Bit 1 */
3254 #define ADC_SMPR2_SMP0_2 ((u32)0x00000004) /* Bit 2 */
3255 
3256 #define ADC_SMPR2_SMP1 ((u32)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */
3257 #define ADC_SMPR2_SMP1_0 ((u32)0x00000008) /* Bit 0 */
3258 #define ADC_SMPR2_SMP1_1 ((u32)0x00000010) /* Bit 1 */
3259 #define ADC_SMPR2_SMP1_2 ((u32)0x00000020) /* Bit 2 */
3260 
3261 #define ADC_SMPR2_SMP2 ((u32)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */
3262 #define ADC_SMPR2_SMP2_0 ((u32)0x00000040) /* Bit 0 */
3263 #define ADC_SMPR2_SMP2_1 ((u32)0x00000080) /* Bit 1 */
3264 #define ADC_SMPR2_SMP2_2 ((u32)0x00000100) /* Bit 2 */
3265 
3266 #define ADC_SMPR2_SMP3 ((u32)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */
3267 #define ADC_SMPR2_SMP3_0 ((u32)0x00000200) /* Bit 0 */
3268 #define ADC_SMPR2_SMP3_1 ((u32)0x00000400) /* Bit 1 */
3269 #define ADC_SMPR2_SMP3_2 ((u32)0x00000800) /* Bit 2 */
3270 
3271 #define ADC_SMPR2_SMP4 ((u32)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */
3272 #define ADC_SMPR2_SMP4_0 ((u32)0x00001000) /* Bit 0 */
3273 #define ADC_SMPR2_SMP4_1 ((u32)0x00002000) /* Bit 1 */
3274 #define ADC_SMPR2_SMP4_2 ((u32)0x00004000) /* Bit 2 */
3275 
3276 #define ADC_SMPR2_SMP5 ((u32)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */
3277 #define ADC_SMPR2_SMP5_0 ((u32)0x00008000) /* Bit 0 */
3278 #define ADC_SMPR2_SMP5_1 ((u32)0x00010000) /* Bit 1 */
3279 #define ADC_SMPR2_SMP5_2 ((u32)0x00020000) /* Bit 2 */
3280 
3281 #define ADC_SMPR2_SMP6 ((u32)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */
3282 #define ADC_SMPR2_SMP6_0 ((u32)0x00040000) /* Bit 0 */
3283 #define ADC_SMPR2_SMP6_1 ((u32)0x00080000) /* Bit 1 */
3284 #define ADC_SMPR2_SMP6_2 ((u32)0x00100000) /* Bit 2 */
3285 
3286 #define ADC_SMPR2_SMP7 ((u32)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */
3287 #define ADC_SMPR2_SMP7_0 ((u32)0x00200000) /* Bit 0 */
3288 #define ADC_SMPR2_SMP7_1 ((u32)0x00400000) /* Bit 1 */
3289 #define ADC_SMPR2_SMP7_2 ((u32)0x00800000) /* Bit 2 */
3290 
3291 #define ADC_SMPR2_SMP8 ((u32)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */
3292 #define ADC_SMPR2_SMP8_0 ((u32)0x01000000) /* Bit 0 */
3293 #define ADC_SMPR2_SMP8_1 ((u32)0x02000000) /* Bit 1 */
3294 #define ADC_SMPR2_SMP8_2 ((u32)0x04000000) /* Bit 2 */
3295 
3296 #define ADC_SMPR2_SMP9 ((u32)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */
3297 #define ADC_SMPR2_SMP9_0 ((u32)0x08000000) /* Bit 0 */
3298 #define ADC_SMPR2_SMP9_1 ((u32)0x10000000) /* Bit 1 */
3299 #define ADC_SMPR2_SMP9_2 ((u32)0x20000000) /* Bit 2 */
3300 
3301 
3302 /****************** Bit definition for ADC_JOFR1 register *******************/
3303 #define ADC_JOFR1_JOFFSET1 ((u16)0x0FFF) /* Data offset for injected channel 1 */
3304 
3305 
3306 /****************** Bit definition for ADC_JOFR2 register *******************/
3307 #define ADC_JOFR2_JOFFSET2 ((u16)0x0FFF) /* Data offset for injected channel 2 */
3308 
3309 
3310 /****************** Bit definition for ADC_JOFR3 register *******************/
3311 #define ADC_JOFR3_JOFFSET3 ((u16)0x0FFF) /* Data offset for injected channel 3 */
3312 
3313 
3314 /****************** Bit definition for ADC_JOFR4 register *******************/
3315 #define ADC_JOFR4_JOFFSET4 ((u16)0x0FFF) /* Data offset for injected channel 4 */
3316 
3317 
3318 /******************* Bit definition for ADC_HTR register ********************/
3319 #define ADC_HTR_HT ((u16)0x0FFF) /* Analog watchdog high threshold */
3320 
3321 
3322 /******************* Bit definition for ADC_LTR register ********************/
3323 #define ADC_LTR_LT ((u16)0x0FFF) /* Analog watchdog low threshold */
3324 
3325 
3326 /******************* Bit definition for ADC_SQR1 register *******************/
3327 #define ADC_SQR1_SQ13 ((u32)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */
3328 #define ADC_SQR1_SQ13_0 ((u32)0x00000001) /* Bit 0 */
3329 #define ADC_SQR1_SQ13_1 ((u32)0x00000002) /* Bit 1 */
3330 #define ADC_SQR1_SQ13_2 ((u32)0x00000004) /* Bit 2 */
3331 #define ADC_SQR1_SQ13_3 ((u32)0x00000008) /* Bit 3 */
3332 #define ADC_SQR1_SQ13_4 ((u32)0x00000010) /* Bit 4 */
3333 
3334 #define ADC_SQR1_SQ14 ((u32)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */
3335 #define ADC_SQR1_SQ14_0 ((u32)0x00000020) /* Bit 0 */
3336 #define ADC_SQR1_SQ14_1 ((u32)0x00000040) /* Bit 1 */
3337 #define ADC_SQR1_SQ14_2 ((u32)0x00000080) /* Bit 2 */
3338 #define ADC_SQR1_SQ14_3 ((u32)0x00000100) /* Bit 3 */
3339 #define ADC_SQR1_SQ14_4 ((u32)0x00000200) /* Bit 4 */
3340 
3341 #define ADC_SQR1_SQ15 ((u32)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */
3342 #define ADC_SQR1_SQ15_0 ((u32)0x00000400) /* Bit 0 */
3343 #define ADC_SQR1_SQ15_1 ((u32)0x00000800) /* Bit 1 */
3344 #define ADC_SQR1_SQ15_2 ((u32)0x00001000) /* Bit 2 */
3345 #define ADC_SQR1_SQ15_3 ((u32)0x00002000) /* Bit 3 */
3346 #define ADC_SQR1_SQ15_4 ((u32)0x00004000) /* Bit 4 */
3347 
3348 #define ADC_SQR1_SQ16 ((u32)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */
3349 #define ADC_SQR1_SQ16_0 ((u32)0x00008000) /* Bit 0 */
3350 #define ADC_SQR1_SQ16_1 ((u32)0x00010000) /* Bit 1 */
3351 #define ADC_SQR1_SQ16_2 ((u32)0x00020000) /* Bit 2 */
3352 #define ADC_SQR1_SQ16_3 ((u32)0x00040000) /* Bit 3 */
3353 #define ADC_SQR1_SQ16_4 ((u32)0x00080000) /* Bit 4 */
3354 
3355 #define ADC_SQR1_L ((u32)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */
3356 #define ADC_SQR1_L_0 ((u32)0x00100000) /* Bit 0 */
3357 #define ADC_SQR1_L_1 ((u32)0x00200000) /* Bit 1 */
3358 #define ADC_SQR1_L_2 ((u32)0x00400000) /* Bit 2 */
3359 #define ADC_SQR1_L_3 ((u32)0x00800000) /* Bit 3 */
3360 
3361 
3362 /******************* Bit definition for ADC_SQR2 register *******************/
3363 #define ADC_SQR2_SQ7 ((u32)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */
3364 #define ADC_SQR2_SQ7_0 ((u32)0x00000001) /* Bit 0 */
3365 #define ADC_SQR2_SQ7_1 ((u32)0x00000002) /* Bit 1 */
3366 #define ADC_SQR2_SQ7_2 ((u32)0x00000004) /* Bit 2 */
3367 #define ADC_SQR2_SQ7_3 ((u32)0x00000008) /* Bit 3 */
3368 #define ADC_SQR2_SQ7_4 ((u32)0x00000010) /* Bit 4 */
3369 
3370 #define ADC_SQR2_SQ8 ((u32)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */
3371 #define ADC_SQR2_SQ8_0 ((u32)0x00000020) /* Bit 0 */
3372 #define ADC_SQR2_SQ8_1 ((u32)0x00000040) /* Bit 1 */
3373 #define ADC_SQR2_SQ8_2 ((u32)0x00000080) /* Bit 2 */
3374 #define ADC_SQR2_SQ8_3 ((u32)0x00000100) /* Bit 3 */
3375 #define ADC_SQR2_SQ8_4 ((u32)0x00000200) /* Bit 4 */
3376 
3377 #define ADC_SQR2_SQ9 ((u32)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */
3378 #define ADC_SQR2_SQ9_0 ((u32)0x00000400) /* Bit 0 */
3379 #define ADC_SQR2_SQ9_1 ((u32)0x00000800) /* Bit 1 */
3380 #define ADC_SQR2_SQ9_2 ((u32)0x00001000) /* Bit 2 */
3381 #define ADC_SQR2_SQ9_3 ((u32)0x00002000) /* Bit 3 */
3382 #define ADC_SQR2_SQ9_4 ((u32)0x00004000) /* Bit 4 */
3383 
3384 #define ADC_SQR2_SQ10 ((u32)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */
3385 #define ADC_SQR2_SQ10_0 ((u32)0x00008000) /* Bit 0 */
3386 #define ADC_SQR2_SQ10_1 ((u32)0x00010000) /* Bit 1 */
3387 #define ADC_SQR2_SQ10_2 ((u32)0x00020000) /* Bit 2 */
3388 #define ADC_SQR2_SQ10_3 ((u32)0x00040000) /* Bit 3 */
3389 #define ADC_SQR2_SQ10_4 ((u32)0x00080000) /* Bit 4 */
3390 
3391 #define ADC_SQR2_SQ11 ((u32)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */
3392 #define ADC_SQR2_SQ11_0 ((u32)0x00100000) /* Bit 0 */
3393 #define ADC_SQR2_SQ11_1 ((u32)0x00200000) /* Bit 1 */
3394 #define ADC_SQR2_SQ11_2 ((u32)0x00400000) /* Bit 2 */
3395 #define ADC_SQR2_SQ11_3 ((u32)0x00800000) /* Bit 3 */
3396 #define ADC_SQR2_SQ11_4 ((u32)0x01000000) /* Bit 4 */
3397 
3398 #define ADC_SQR2_SQ12 ((u32)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */
3399 #define ADC_SQR2_SQ12_0 ((u32)0x02000000) /* Bit 0 */
3400 #define ADC_SQR2_SQ12_1 ((u32)0x04000000) /* Bit 1 */
3401 #define ADC_SQR2_SQ12_2 ((u32)0x08000000) /* Bit 2 */
3402 #define ADC_SQR2_SQ12_3 ((u32)0x10000000) /* Bit 3 */
3403 #define ADC_SQR2_SQ12_4 ((u32)0x20000000) /* Bit 4 */
3404 
3405 
3406 /******************* Bit definition for ADC_SQR3 register *******************/
3407 #define ADC_SQR3_SQ1 ((u32)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */
3408 #define ADC_SQR3_SQ1_0 ((u32)0x00000001) /* Bit 0 */
3409 #define ADC_SQR3_SQ1_1 ((u32)0x00000002) /* Bit 1 */
3410 #define ADC_SQR3_SQ1_2 ((u32)0x00000004) /* Bit 2 */
3411 #define ADC_SQR3_SQ1_3 ((u32)0x00000008) /* Bit 3 */
3412 #define ADC_SQR3_SQ1_4 ((u32)0x00000010) /* Bit 4 */
3413 
3414 #define ADC_SQR3_SQ2 ((u32)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */
3415 #define ADC_SQR3_SQ2_0 ((u32)0x00000020) /* Bit 0 */
3416 #define ADC_SQR3_SQ2_1 ((u32)0x00000040) /* Bit 1 */
3417 #define ADC_SQR3_SQ2_2 ((u32)0x00000080) /* Bit 2 */
3418 #define ADC_SQR3_SQ2_3 ((u32)0x00000100) /* Bit 3 */
3419 #define ADC_SQR3_SQ2_4 ((u32)0x00000200) /* Bit 4 */
3420 
3421 #define ADC_SQR3_SQ3 ((u32)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */
3422 #define ADC_SQR3_SQ3_0 ((u32)0x00000400) /* Bit 0 */
3423 #define ADC_SQR3_SQ3_1 ((u32)0x00000800) /* Bit 1 */
3424 #define ADC_SQR3_SQ3_2 ((u32)0x00001000) /* Bit 2 */
3425 #define ADC_SQR3_SQ3_3 ((u32)0x00002000) /* Bit 3 */
3426 #define ADC_SQR3_SQ3_4 ((u32)0x00004000) /* Bit 4 */
3427 
3428 #define ADC_SQR3_SQ4 ((u32)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */
3429 #define ADC_SQR3_SQ4_0 ((u32)0x00008000) /* Bit 0 */
3430 #define ADC_SQR3_SQ4_1 ((u32)0x00010000) /* Bit 1 */
3431 #define ADC_SQR3_SQ4_2 ((u32)0x00020000) /* Bit 2 */
3432 #define ADC_SQR3_SQ4_3 ((u32)0x00040000) /* Bit 3 */
3433 #define ADC_SQR3_SQ4_4 ((u32)0x00080000) /* Bit 4 */
3434 
3435 #define ADC_SQR3_SQ5 ((u32)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */
3436 #define ADC_SQR3_SQ5_0 ((u32)0x00100000) /* Bit 0 */
3437 #define ADC_SQR3_SQ5_1 ((u32)0x00200000) /* Bit 1 */
3438 #define ADC_SQR3_SQ5_2 ((u32)0x00400000) /* Bit 2 */
3439 #define ADC_SQR3_SQ5_3 ((u32)0x00800000) /* Bit 3 */
3440 #define ADC_SQR3_SQ5_4 ((u32)0x01000000) /* Bit 4 */
3441 
3442 #define ADC_SQR3_SQ6 ((u32)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */
3443 #define ADC_SQR3_SQ6_0 ((u32)0x02000000) /* Bit 0 */
3444 #define ADC_SQR3_SQ6_1 ((u32)0x04000000) /* Bit 1 */
3445 #define ADC_SQR3_SQ6_2 ((u32)0x08000000) /* Bit 2 */
3446 #define ADC_SQR3_SQ6_3 ((u32)0x10000000) /* Bit 3 */
3447 #define ADC_SQR3_SQ6_4 ((u32)0x20000000) /* Bit 4 */
3448 
3449 
3450 /******************* Bit definition for ADC_JSQR register *******************/
3451 #define ADC_JSQR_JSQ1 ((u32)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */
3452 #define ADC_JSQR_JSQ1_0 ((u32)0x00000001) /* Bit 0 */
3453 #define ADC_JSQR_JSQ1_1 ((u32)0x00000002) /* Bit 1 */
3454 #define ADC_JSQR_JSQ1_2 ((u32)0x00000004) /* Bit 2 */
3455 #define ADC_JSQR_JSQ1_3 ((u32)0x00000008) /* Bit 3 */
3456 #define ADC_JSQR_JSQ1_4 ((u32)0x00000010) /* Bit 4 */
3457 
3458 #define ADC_JSQR_JSQ2 ((u32)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */
3459 #define ADC_JSQR_JSQ2_0 ((u32)0x00000020) /* Bit 0 */
3460 #define ADC_JSQR_JSQ2_1 ((u32)0x00000040) /* Bit 1 */
3461 #define ADC_JSQR_JSQ2_2 ((u32)0x00000080) /* Bit 2 */
3462 #define ADC_JSQR_JSQ2_3 ((u32)0x00000100) /* Bit 3 */
3463 #define ADC_JSQR_JSQ2_4 ((u32)0x00000200) /* Bit 4 */
3464 
3465 #define ADC_JSQR_JSQ3 ((u32)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */
3466 #define ADC_JSQR_JSQ3_0 ((u32)0x00000400) /* Bit 0 */
3467 #define ADC_JSQR_JSQ3_1 ((u32)0x00000800) /* Bit 1 */
3468 #define ADC_JSQR_JSQ3_2 ((u32)0x00001000) /* Bit 2 */
3469 #define ADC_JSQR_JSQ3_3 ((u32)0x00002000) /* Bit 3 */
3470 #define ADC_JSQR_JSQ3_4 ((u32)0x00004000) /* Bit 4 */
3471 
3472 #define ADC_JSQR_JSQ4 ((u32)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */
3473 #define ADC_JSQR_JSQ4_0 ((u32)0x00008000) /* Bit 0 */
3474 #define ADC_JSQR_JSQ4_1 ((u32)0x00010000) /* Bit 1 */
3475 #define ADC_JSQR_JSQ4_2 ((u32)0x00020000) /* Bit 2 */
3476 #define ADC_JSQR_JSQ4_3 ((u32)0x00040000) /* Bit 3 */
3477 #define ADC_JSQR_JSQ4_4 ((u32)0x00080000) /* Bit 4 */
3478 
3479 #define ADC_JSQR_JL ((u32)0x00300000) /* JL[1:0] bits (Injected Sequence length) */
3480 #define ADC_JSQR_JL_0 ((u32)0x00100000) /* Bit 0 */
3481 #define ADC_JSQR_JL_1 ((u32)0x00200000) /* Bit 1 */
3482 
3483 
3484 /******************* Bit definition for ADC_JDR1 register *******************/
3485 #define ADC_JDR1_JDATA ((u16)0xFFFF) /* Injected data */
3486 
3487 
3488 /******************* Bit definition for ADC_JDR2 register *******************/
3489 #define ADC_JDR2_JDATA ((u16)0xFFFF) /* Injected data */
3490 
3491 
3492 /******************* Bit definition for ADC_JDR3 register *******************/
3493 #define ADC_JDR3_JDATA ((u16)0xFFFF) /* Injected data */
3494 
3495 
3496 /******************* Bit definition for ADC_JDR4 register *******************/
3497 #define ADC_JDR4_JDATA ((u16)0xFFFF) /* Injected data */
3498 
3499 
3500 /******************** Bit definition for ADC_DR register ********************/
3501 #define ADC_DR_DATA ((u32)0x0000FFFF) /* Regular data */
3502 #define ADC_DR_ADC2DATA ((u32)0xFFFF0000) /* ADC2 data */
3503 
3504 
3505 
3506 /******************************************************************************/
3507 /* */
3508 /* Digital to Analog Converter */
3509 /* */
3510 /******************************************************************************/
3511 
3512 /******************** Bit definition for DAC_CR register ********************/
3513 #define DAC_CR_EN1 ((u32)0x00000001) /* DAC channel1 enable */
3514 #define DAC_CR_BOFF1 ((u32)0x00000002) /* DAC channel1 output buffer disable */
3515 #define DAC_CR_TEN1 ((u32)0x00000004) /* DAC channel1 Trigger enable */
3516 
3517 #define DAC_CR_TSEL1 ((u32)0x00000038) /* TSEL1[2:0] (DAC channel1 Trigger selection) */
3518 #define DAC_CR_TSEL1_0 ((u32)0x00000008) /* Bit 0 */
3519 #define DAC_CR_TSEL1_1 ((u32)0x00000010) /* Bit 1 */
3520 #define DAC_CR_TSEL1_2 ((u32)0x00000020) /* Bit 2 */
3521 
3522 #define DAC_CR_WAVE1 ((u32)0x000000C0) /* WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
3523 #define DAC_CR_WAVE1_0 ((u32)0x00000040) /* Bit 0 */
3524 #define DAC_CR_WAVE1_1 ((u32)0x00000080) /* Bit 1 */
3525 
3526 #define DAC_CR_MAMP1 ((u32)0x00000F00) /* MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
3527 #define DAC_CR_MAMP1_0 ((u32)0x00000100) /* Bit 0 */
3528 #define DAC_CR_MAMP1_1 ((u32)0x00000200) /* Bit 1 */
3529 #define DAC_CR_MAMP1_2 ((u32)0x00000400) /* Bit 2 */
3530 #define DAC_CR_MAMP1_3 ((u32)0x00000800) /* Bit 3 */
3531 
3532 #define DAC_CR_DMAEN1 ((u32)0x00001000) /* DAC channel1 DMA enable */
3533 #define DAC_CR_EN2 ((u32)0x00010000) /* DAC channel2 enable */
3534 #define DAC_CR_BOFF2 ((u32)0x00020000) /* DAC channel2 output buffer disable */
3535 #define DAC_CR_TEN2 ((u32)0x00040000) /* DAC channel2 Trigger enable */
3536 
3537 #define DAC_CR_TSEL2 ((u32)0x00380000) /* TSEL2[2:0] (DAC channel2 Trigger selection) */
3538 #define DAC_CR_TSEL2_0 ((u32)0x00080000) /* Bit 0 */
3539 #define DAC_CR_TSEL2_1 ((u32)0x00100000) /* Bit 1 */
3540 #define DAC_CR_TSEL2_2 ((u32)0x00200000) /* Bit 2 */
3541 
3542 #define DAC_CR_WAVE2 ((u32)0x00C00000) /* WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
3543 #define DAC_CR_WAVE2_0 ((u32)0x00400000) /* Bit 0 */
3544 #define DAC_CR_WAVE2_1 ((u32)0x00800000) /* Bit 1 */
3545 
3546 #define DAC_CR_MAMP2 ((u32)0x0F000000) /* MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
3547 #define DAC_CR_MAMP2_0 ((u32)0x01000000) /* Bit 0 */
3548 #define DAC_CR_MAMP2_1 ((u32)0x02000000) /* Bit 1 */
3549 #define DAC_CR_MAMP2_2 ((u32)0x04000000) /* Bit 2 */
3550 #define DAC_CR_MAMP2_3 ((u32)0x08000000) /* Bit 3 */
3551 
3552 #define DAC_CR_DMAEN2 ((u32)0x10000000) /* DAC channel2 DMA enabled */
3553 
3554 
3555 /***************** Bit definition for DAC_SWTRIGR register ******************/
3556 #define DAC_SWTRIGR_SWTRIG1 ((u8)0x01) /* DAC channel1 software trigger */
3557 #define DAC_SWTRIGR_SWTRIG2 ((u8)0x02) /* DAC channel2 software trigger */
3558 
3559 
3560 /***************** Bit definition for DAC_DHR12R1 register ******************/
3561 #define DAC_DHR12R1_DACC1DHR ((u16)0x0FFF) /* DAC channel1 12-bit Right aligned data */
3562 
3563 
3564 /***************** Bit definition for DAC_DHR12L1 register ******************/
3565 #define DAC_DHR12L1_DACC1DHR ((u16)0xFFF0) /* DAC channel1 12-bit Left aligned data */
3566 
3567 
3568 /****************** Bit definition for DAC_DHR8R1 register ******************/
3569 #define DAC_DHR8R1_DACC1DHR ((u8)0xFF) /* DAC channel1 8-bit Right aligned data */
3570 
3571 
3572 /***************** Bit definition for DAC_DHR12R2 register ******************/
3573 #define DAC_DHR12R2_DACC2DHR ((u16)0x0FFF) /* DAC channel2 12-bit Right aligned data */
3574 
3575 
3576 /***************** Bit definition for DAC_DHR12L2 register ******************/
3577 #define DAC_DHR12L2_DACC2DHR ((u16)0xFFF0) /* DAC channel2 12-bit Left aligned data */
3578 
3579 
3580 /****************** Bit definition for DAC_DHR8R2 register ******************/
3581 #define DAC_DHR8R2_DACC2DHR ((u8)0xFF) /* DAC channel2 8-bit Right aligned data */
3582 
3583 
3584 /***************** Bit definition for DAC_DHR12RD register ******************/
3585 #define DAC_DHR12RD_DACC1DHR ((u32)0x00000FFF) /* DAC channel1 12-bit Right aligned data */
3586 #define DAC_DHR12RD_DACC2DHR ((u32)0x0FFF0000) /* DAC channel2 12-bit Right aligned data */
3587 
3588 
3589 /***************** Bit definition for DAC_DHR12LD register ******************/
3590 #define DAC_DHR12LD_DACC1DHR ((u32)0x0000FFF0) /* DAC channel1 12-bit Left aligned data */
3591 #define DAC_DHR12LD_DACC2DHR ((u32)0xFFF00000) /* DAC channel2 12-bit Left aligned data */
3592 
3593 
3594 /****************** Bit definition for DAC_DHR8RD register ******************/
3595 #define DAC_DHR8RD_DACC1DHR ((u16)0x00FF) /* DAC channel1 8-bit Right aligned data */
3596 #define DAC_DHR8RD_DACC2DHR ((u16)0xFF00) /* DAC channel2 8-bit Right aligned data */
3597 
3598 
3599 /******************* Bit definition for DAC_DOR1 register *******************/
3600 #define DAC_DOR1_DACC1DOR ((u16)0x0FFF) /* DAC channel1 data output */
3601 
3602 
3603 /******************* Bit definition for DAC_DOR2 register *******************/
3604 #define DAC_DOR2_DACC2DOR ((u16)0x0FFF) /* DAC channel2 data output */
3605 
3606 
3607 
3608 /******************************************************************************/
3609 /* */
3610 /* TIM */
3611 /* */
3612 /******************************************************************************/
3613 
3614 /******************* Bit definition for TIM_CR1 register ********************/
3615 #define TIM_CR1_CEN ((u16)0x0001) /* Counter enable */
3616 #define TIM_CR1_UDIS ((u16)0x0002) /* Update disable */
3617 #define TIM_CR1_URS ((u16)0x0004) /* Update request source */
3618 #define TIM_CR1_OPM ((u16)0x0008) /* One pulse mode */
3619 #define TIM_CR1_DIR ((u16)0x0010) /* Direction */
3620 
3621 #define TIM_CR1_CMS ((u16)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */
3622 #define TIM_CR1_CMS_0 ((u16)0x0020) /* Bit 0 */
3623 #define TIM_CR1_CMS_1 ((u16)0x0040) /* Bit 1 */
3624 
3625 #define TIM_CR1_ARPE ((u16)0x0080) /* Auto-reload preload enable */
3626 
3627 #define TIM_CR1_CKD ((u16)0x0300) /* CKD[1:0] bits (clock division) */
3628 #define TIM_CR1_CKD_0 ((u16)0x0100) /* Bit 0 */
3629 #define TIM_CR1_CKD_1 ((u16)0x0200) /* Bit 1 */
3630 
3631 
3632 /******************* Bit definition for TIM_CR2 register ********************/
3633 #define TIM_CR2_CCPC ((u16)0x0001) /* Capture/Compare Preloaded Control */
3634 #define TIM_CR2_CCUS ((u16)0x0004) /* Capture/Compare Control Update Selection */
3635 #define TIM_CR2_CCDS ((u16)0x0008) /* Capture/Compare DMA Selection */
3636 
3637 #define TIM_CR2_MMS ((u16)0x0070) /* MMS[2:0] bits (Master Mode Selection) */
3638 #define TIM_CR2_MMS_0 ((u16)0x0010) /* Bit 0 */
3639 #define TIM_CR2_MMS_1 ((u16)0x0020) /* Bit 1 */
3640 #define TIM_CR2_MMS_2 ((u16)0x0040) /* Bit 2 */
3641 
3642 #define TIM_CR2_TI1S ((u16)0x0080) /* TI1 Selection */
3643 #define TIM_CR2_OIS1 ((u16)0x0100) /* Output Idle state 1 (OC1 output) */
3644 #define TIM_CR2_OIS1N ((u16)0x0200) /* Output Idle state 1 (OC1N output) */
3645 #define TIM_CR2_OIS2 ((u16)0x0400) /* Output Idle state 2 (OC2 output) */
3646 #define TIM_CR2_OIS2N ((u16)0x0800) /* Output Idle state 2 (OC2N output) */
3647 #define TIM_CR2_OIS3 ((u16)0x1000) /* Output Idle state 3 (OC3 output) */
3648 #define TIM_CR2_OIS3N ((u16)0x2000) /* Output Idle state 3 (OC3N output) */
3649 #define TIM_CR2_OIS4 ((u16)0x4000) /* Output Idle state 4 (OC4 output) */
3650 
3651 
3652 /******************* Bit definition for TIM_SMCR register *******************/
3653 #define TIM_SMCR_SMS ((u16)0x0007) /* SMS[2:0] bits (Slave mode selection) */
3654 #define TIM_SMCR_SMS_0 ((u16)0x0001) /* Bit 0 */
3655 #define TIM_SMCR_SMS_1 ((u16)0x0002) /* Bit 1 */
3656 #define TIM_SMCR_SMS_2 ((u16)0x0004) /* Bit 2 */
3657 
3658 #define TIM_SMCR_TS ((u16)0x0070) /* TS[2:0] bits (Trigger selection) */
3659 #define TIM_SMCR_TS_0 ((u16)0x0010) /* Bit 0 */
3660 #define TIM_SMCR_TS_1 ((u16)0x0020) /* Bit 1 */
3661 #define TIM_SMCR_TS_2 ((u16)0x0040) /* Bit 2 */
3662 
3663 #define TIM_SMCR_MSM ((u16)0x0080) /* Master/slave mode */
3664 
3665 #define TIM_SMCR_ETF ((u16)0x0F00) /* ETF[3:0] bits (External trigger filter) */
3666 #define TIM_SMCR_ETF_0 ((u16)0x0100) /* Bit 0 */
3667 #define TIM_SMCR_ETF_1 ((u16)0x0200) /* Bit 1 */
3668 #define TIM_SMCR_ETF_2 ((u16)0x0400) /* Bit 2 */
3669 #define TIM_SMCR_ETF_3 ((u16)0x0800) /* Bit 3 */
3670 
3671 #define TIM_SMCR_ETPS ((u16)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */
3672 #define TIM_SMCR_ETPS_0 ((u16)0x1000) /* Bit 0 */
3673 #define TIM_SMCR_ETPS_1 ((u16)0x2000) /* Bit 1 */
3674 
3675 #define TIM_SMCR_ECE ((u16)0x4000) /* External clock enable */
3676 #define TIM_SMCR_ETP ((u16)0x8000) /* External trigger polarity */
3677 
3678 
3679 /******************* Bit definition for TIM_DIER register *******************/
3680 #define TIM_DIER_UIE ((u16)0x0001) /* Update interrupt enable */
3681 #define TIM_DIER_CC1IE ((u16)0x0002) /* Capture/Compare 1 interrupt enable */
3682 #define TIM_DIER_CC2IE ((u16)0x0004) /* Capture/Compare 2 interrupt enable */
3683 #define TIM_DIER_CC3IE ((u16)0x0008) /* Capture/Compare 3 interrupt enable */
3684 #define TIM_DIER_CC4IE ((u16)0x0010) /* Capture/Compare 4 interrupt enable */
3685 #define TIM_DIER_COMIE ((u16)0x0020) /* COM interrupt enable */
3686 #define TIM_DIER_TIE ((u16)0x0040) /* Trigger interrupt enable */
3687 #define TIM_DIER_BIE ((u16)0x0080) /* Break interrupt enable */
3688 #define TIM_DIER_UDE ((u16)0x0100) /* Update DMA request enable */
3689 #define TIM_DIER_CC1DE ((u16)0x0200) /* Capture/Compare 1 DMA request enable */
3690 #define TIM_DIER_CC2DE ((u16)0x0400) /* Capture/Compare 2 DMA request enable */
3691 #define TIM_DIER_CC3DE ((u16)0x0800) /* Capture/Compare 3 DMA request enable */
3692 #define TIM_DIER_CC4DE ((u16)0x1000) /* Capture/Compare 4 DMA request enable */
3693 #define TIM_DIER_COMDE ((u16)0x2000) /* COM DMA request enable */
3694 #define TIM_DIER_TDE ((u16)0x4000) /* Trigger DMA request enable */
3695 
3696 
3697 /******************** Bit definition for TIM_SR register ********************/
3698 #define TIM_SR_UIF ((u16)0x0001) /* Update interrupt Flag */
3699 #define TIM_SR_CC1IF ((u16)0x0002) /* Capture/Compare 1 interrupt Flag */
3700 #define TIM_SR_CC2IF ((u16)0x0004) /* Capture/Compare 2 interrupt Flag */
3701 #define TIM_SR_CC3IF ((u16)0x0008) /* Capture/Compare 3 interrupt Flag */
3702 #define TIM_SR_CC4IF ((u16)0x0010) /* Capture/Compare 4 interrupt Flag */
3703 #define TIM_SR_COMIF ((u16)0x0020) /* COM interrupt Flag */
3704 #define TIM_SR_TIF ((u16)0x0040) /* Trigger interrupt Flag */
3705 #define TIM_SR_BIF ((u16)0x0080) /* Break interrupt Flag */
3706 #define TIM_SR_CC1OF ((u16)0x0200) /* Capture/Compare 1 Overcapture Flag */
3707 #define TIM_SR_CC2OF ((u16)0x0400) /* Capture/Compare 2 Overcapture Flag */
3708 #define TIM_SR_CC3OF ((u16)0x0800) /* Capture/Compare 3 Overcapture Flag */
3709 #define TIM_SR_CC4OF ((u16)0x1000) /* Capture/Compare 4 Overcapture Flag */
3710 
3711 
3712 /******************* Bit definition for TIM_EGR register ********************/
3713 #define TIM_EGR_UG ((u8)0x01) /* Update Generation */
3714 #define TIM_EGR_CC1G ((u8)0x02) /* Capture/Compare 1 Generation */
3715 #define TIM_EGR_CC2G ((u8)0x04) /* Capture/Compare 2 Generation */
3716 #define TIM_EGR_CC3G ((u8)0x08) /* Capture/Compare 3 Generation */
3717 #define TIM_EGR_CC4G ((u8)0x10) /* Capture/Compare 4 Generation */
3718 #define TIM_EGR_COMG ((u8)0x20) /* Capture/Compare Control Update Generation */
3719 #define TIM_EGR_TG ((u8)0x40) /* Trigger Generation */
3720 #define TIM_EGR_BG ((u8)0x80) /* Break Generation */
3721 
3722 
3723 /****************** Bit definition for TIM_CCMR1 register *******************/
3724 #define TIM_CCMR1_CC1S ((u16)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */
3725 #define TIM_CCMR1_CC1S_0 ((u16)0x0001) /* Bit 0 */
3726 #define TIM_CCMR1_CC1S_1 ((u16)0x0002) /* Bit 1 */
3727 
3728 #define TIM_CCMR1_OC1FE ((u16)0x0004) /* Output Compare 1 Fast enable */
3729 #define TIM_CCMR1_OC1PE ((u16)0x0008) /* Output Compare 1 Preload enable */
3730 
3731 #define TIM_CCMR1_OC1M ((u16)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */
3732 #define TIM_CCMR1_OC1M_0 ((u16)0x0010) /* Bit 0 */
3733 #define TIM_CCMR1_OC1M_1 ((u16)0x0020) /* Bit 1 */
3734 #define TIM_CCMR1_OC1M_2 ((u16)0x0040) /* Bit 2 */
3735 
3736 #define TIM_CCMR1_OC1CE ((u16)0x0080) /* Output Compare 1Clear Enable */
3737 
3738 #define TIM_CCMR1_CC2S ((u16)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */
3739 #define TIM_CCMR1_CC2S_0 ((u16)0x0100) /* Bit 0 */
3740 #define TIM_CCMR1_CC2S_1 ((u16)0x0200) /* Bit 1 */
3741 
3742 #define TIM_CCMR1_OC2FE ((u16)0x0400) /* Output Compare 2 Fast enable */
3743 #define TIM_CCMR1_OC2PE ((u16)0x0800) /* Output Compare 2 Preload enable */
3744 
3745 #define TIM_CCMR1_OC2M ((u16)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */
3746 #define TIM_CCMR1_OC2M_0 ((u16)0x1000) /* Bit 0 */
3747 #define TIM_CCMR1_OC2M_1 ((u16)0x2000) /* Bit 1 */
3748 #define TIM_CCMR1_OC2M_2 ((u16)0x4000) /* Bit 2 */
3749 
3750 #define TIM_CCMR1_OC2CE ((u16)0x8000) /* Output Compare 2 Clear Enable */
3751 
3752 /*----------------------------------------------------------------------------*/
3753 
3754 #define TIM_CCMR1_IC1PSC ((u16)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
3755 #define TIM_CCMR1_IC1PSC_0 ((u16)0x0004) /* Bit 0 */
3756 #define TIM_CCMR1_IC1PSC_1 ((u16)0x0008) /* Bit 1 */
3757 
3758 #define TIM_CCMR1_IC1F ((u16)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */
3759 #define TIM_CCMR1_IC1F_0 ((u16)0x0010) /* Bit 0 */
3760 #define TIM_CCMR1_IC1F_1 ((u16)0x0020) /* Bit 1 */
3761 #define TIM_CCMR1_IC1F_2 ((u16)0x0040) /* Bit 2 */
3762 #define TIM_CCMR1_IC1F_3 ((u16)0x0080) /* Bit 3 */
3763 
3764 #define TIM_CCMR1_IC2PSC ((u16)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
3765 #define TIM_CCMR1_IC2PSC_0 ((u16)0x0400) /* Bit 0 */
3766 #define TIM_CCMR1_IC2PSC_1 ((u16)0x0800) /* Bit 1 */
3767 
3768 #define TIM_CCMR1_IC2F ((u16)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */
3769 #define TIM_CCMR1_IC2F_0 ((u16)0x1000) /* Bit 0 */
3770 #define TIM_CCMR1_IC2F_1 ((u16)0x2000) /* Bit 1 */
3771 #define TIM_CCMR1_IC2F_2 ((u16)0x4000) /* Bit 2 */
3772 #define TIM_CCMR1_IC2F_3 ((u16)0x8000) /* Bit 3 */
3773 
3774 
3775 /****************** Bit definition for TIM_CCMR2 register *******************/
3776 #define TIM_CCMR2_CC3S ((u16)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */
3777 #define TIM_CCMR2_CC3S_0 ((u16)0x0001) /* Bit 0 */
3778 #define TIM_CCMR2_CC3S_1 ((u16)0x0002) /* Bit 1 */
3779 
3780 #define TIM_CCMR2_OC3FE ((u16)0x0004) /* Output Compare 3 Fast enable */
3781 #define TIM_CCMR2_OC3PE ((u16)0x0008) /* Output Compare 3 Preload enable */
3782 
3783 #define TIM_CCMR2_OC3M ((u16)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */
3784 #define TIM_CCMR2_OC3M_0 ((u16)0x0010) /* Bit 0 */
3785 #define TIM_CCMR2_OC3M_1 ((u16)0x0020) /* Bit 1 */
3786 #define TIM_CCMR2_OC3M_2 ((u16)0x0040) /* Bit 2 */
3787 
3788 #define TIM_CCMR2_OC3CE ((u16)0x0080) /* Output Compare 3 Clear Enable */
3789 
3790 #define TIM_CCMR2_CC4S ((u16)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */
3791 #define TIM_CCMR2_CC4S_0 ((u16)0x0100) /* Bit 0 */
3792 #define TIM_CCMR2_CC4S_1 ((u16)0x0200) /* Bit 1 */
3793 
3794 #define TIM_CCMR2_OC4FE ((u16)0x0400) /* Output Compare 4 Fast enable */
3795 #define TIM_CCMR2_OC4PE ((u16)0x0800) /* Output Compare 4 Preload enable */
3796 
3797 #define TIM_CCMR2_OC4M ((u16)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */
3798 #define TIM_CCMR2_OC4M_0 ((u16)0x1000) /* Bit 0 */
3799 #define TIM_CCMR2_OC4M_1 ((u16)0x2000) /* Bit 1 */
3800 #define TIM_CCMR2_OC4M_2 ((u16)0x4000) /* Bit 2 */
3801 
3802 #define TIM_CCMR2_OC4CE ((u16)0x8000) /* Output Compare 4 Clear Enable */
3803 
3804 /*----------------------------------------------------------------------------*/
3805 
3806 #define TIM_CCMR2_IC3PSC ((u16)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
3807 #define TIM_CCMR2_IC3PSC_0 ((u16)0x0004) /* Bit 0 */
3808 #define TIM_CCMR2_IC3PSC_1 ((u16)0x0008) /* Bit 1 */
3809 
3810 #define TIM_CCMR2_IC3F ((u16)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */
3811 #define TIM_CCMR2_IC3F_0 ((u16)0x0010) /* Bit 0 */
3812 #define TIM_CCMR2_IC3F_1 ((u16)0x0020) /* Bit 1 */
3813 #define TIM_CCMR2_IC3F_2 ((u16)0x0040) /* Bit 2 */
3814 #define TIM_CCMR2_IC3F_3 ((u16)0x0080) /* Bit 3 */
3815 
3816 #define TIM_CCMR2_IC4PSC ((u16)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
3817 #define TIM_CCMR2_IC4PSC_0 ((u16)0x0400) /* Bit 0 */
3818 #define TIM_CCMR2_IC4PSC_1 ((u16)0x0800) /* Bit 1 */
3819 
3820 #define TIM_CCMR2_IC4F ((u16)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */
3821 #define TIM_CCMR2_IC4F_0 ((u16)0x1000) /* Bit 0 */
3822 #define TIM_CCMR2_IC4F_1 ((u16)0x2000) /* Bit 1 */
3823 #define TIM_CCMR2_IC4F_2 ((u16)0x4000) /* Bit 2 */
3824 #define TIM_CCMR2_IC4F_3 ((u16)0x8000) /* Bit 3 */
3825 
3826 
3827 /******************* Bit definition for TIM_CCER register *******************/
3828 #define TIM_CCER_CC1E ((u16)0x0001) /* Capture/Compare 1 output enable */
3829 #define TIM_CCER_CC1P ((u16)0x0002) /* Capture/Compare 1 output Polarity */
3830 #define TIM_CCER_CC1NE ((u16)0x0004) /* Capture/Compare 1 Complementary output enable */
3831 #define TIM_CCER_CC1NP ((u16)0x0008) /* Capture/Compare 1 Complementary output Polarity */
3832 #define TIM_CCER_CC2E ((u16)0x0010) /* Capture/Compare 2 output enable */
3833 #define TIM_CCER_CC2P ((u16)0x0020) /* Capture/Compare 2 output Polarity */
3834 #define TIM_CCER_CC2NE ((u16)0x0040) /* Capture/Compare 2 Complementary output enable */
3835 #define TIM_CCER_CC2NP ((u16)0x0080) /* Capture/Compare 2 Complementary output Polarity */
3836 #define TIM_CCER_CC3E ((u16)0x0100) /* Capture/Compare 3 output enable */
3837 #define TIM_CCER_CC3P ((u16)0x0200) /* Capture/Compare 3 output Polarity */
3838 #define TIM_CCER_CC3NE ((u16)0x0400) /* Capture/Compare 3 Complementary output enable */
3839 #define TIM_CCER_CC3NP ((u16)0x0800) /* Capture/Compare 3 Complementary output Polarity */
3840 #define TIM_CCER_CC4E ((u16)0x1000) /* Capture/Compare 4 output enable */
3841 #define TIM_CCER_CC4P ((u16)0x2000) /* Capture/Compare 4 output Polarity */
3842 
3843 
3844 /******************* Bit definition for TIM_CNT register ********************/
3845 #define TIM_CNT_CNT ((u16)0xFFFF) /* Counter Value */
3846 
3847 
3848 /******************* Bit definition for TIM_PSC register ********************/
3849 #define TIM_PSC_PSC ((u16)0xFFFF) /* Prescaler Value */
3850 
3851 
3852 /******************* Bit definition for TIM_ARR register ********************/
3853 #define TIM_ARR_ARR ((u16)0xFFFF) /* actual auto-reload Value */
3854 
3855 
3856 /******************* Bit definition for TIM_RCR register ********************/
3857 #define TIM_RCR_REP ((u8)0xFF) /* Repetition Counter Value */
3858 
3859 
3860 /******************* Bit definition for TIM_CCR1 register *******************/
3861 #define TIM_CCR1_CCR1 ((u16)0xFFFF) /* Capture/Compare 1 Value */
3862 
3863 
3864 /******************* Bit definition for TIM_CCR2 register *******************/
3865 #define TIM_CCR2_CCR2 ((u16)0xFFFF) /* Capture/Compare 2 Value */
3866 
3867 
3868 /******************* Bit definition for TIM_CCR3 register *******************/
3869 #define TIM_CCR3_CCR3 ((u16)0xFFFF) /* Capture/Compare 3 Value */
3870 
3871 
3872 /******************* Bit definition for TIM_CCR4 register *******************/
3873 #define TIM_CCR4_CCR4 ((u16)0xFFFF) /* Capture/Compare 4 Value */
3874 
3875 
3876 /******************* Bit definition for TIM_BDTR register *******************/
3877 #define TIM_BDTR_DTG ((u16)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */
3878 #define TIM_BDTR_DTG_0 ((u16)0x0001) /* Bit 0 */
3879 #define TIM_BDTR_DTG_1 ((u16)0x0002) /* Bit 1 */
3880 #define TIM_BDTR_DTG_2 ((u16)0x0004) /* Bit 2 */
3881 #define TIM_BDTR_DTG_3 ((u16)0x0008) /* Bit 3 */
3882 #define TIM_BDTR_DTG_4 ((u16)0x0010) /* Bit 4 */
3883 #define TIM_BDTR_DTG_5 ((u16)0x0020) /* Bit 5 */
3884 #define TIM_BDTR_DTG_6 ((u16)0x0040) /* Bit 6 */
3885 #define TIM_BDTR_DTG_7 ((u16)0x0080) /* Bit 7 */
3886 
3887 #define TIM_BDTR_LOCK ((u16)0x0300) /* LOCK[1:0] bits (Lock Configuration) */
3888 #define TIM_BDTR_LOCK_0 ((u16)0x0100) /* Bit 0 */
3889 #define TIM_BDTR_LOCK_1 ((u16)0x0200) /* Bit 1 */
3890 
3891 #define TIM_BDTR_OSSI ((u16)0x0400) /* Off-State Selection for Idle mode */
3892 #define TIM_BDTR_OSSR ((u16)0x0800) /* Off-State Selection for Run mode */
3893 #define TIM_BDTR_BKE ((u16)0x1000) /* Break enable */
3894 #define TIM_BDTR_BKP ((u16)0x2000) /* Break Polarity */
3895 #define TIM_BDTR_AOE ((u16)0x4000) /* Automatic Output enable */
3896 #define TIM_BDTR_MOE ((u16)0x8000) /* Main Output enable */
3897 
3898 
3899 /******************* Bit definition for TIM_DCR register ********************/
3900 #define TIM_DCR_DBA ((u16)0x001F) /* DBA[4:0] bits (DMA Base Address) */
3901 #define TIM_DCR_DBA_0 ((u16)0x0001) /* Bit 0 */
3902 #define TIM_DCR_DBA_1 ((u16)0x0002) /* Bit 1 */
3903 #define TIM_DCR_DBA_2 ((u16)0x0004) /* Bit 2 */
3904 #define TIM_DCR_DBA_3 ((u16)0x0008) /* Bit 3 */
3905 #define TIM_DCR_DBA_4 ((u16)0x0010) /* Bit 4 */
3906 
3907 #define TIM_DCR_DBL ((u16)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */
3908 #define TIM_DCR_DBL_0 ((u16)0x0100) /* Bit 0 */
3909 #define TIM_DCR_DBL_1 ((u16)0x0200) /* Bit 1 */
3910 #define TIM_DCR_DBL_2 ((u16)0x0400) /* Bit 2 */
3911 #define TIM_DCR_DBL_3 ((u16)0x0800) /* Bit 3 */
3912 #define TIM_DCR_DBL_4 ((u16)0x1000) /* Bit 4 */
3913 
3914 
3915 /******************* Bit definition for TIM_DMAR register *******************/
3916 #define TIM_DMAR_DMAB ((u16)0xFFFF) /* DMA register for burst accesses */
3917 
3918 
3919 
3920 /******************************************************************************/
3921 /* */
3922 /* Real-Time Clock */
3923 /* */
3924 /******************************************************************************/
3925 
3926 /******************* Bit definition for RTC_CRH register ********************/
3927 #define RTC_CRH_SECIE ((u8)0x01) /* Second Interrupt Enable */
3928 #define RTC_CRH_ALRIE ((u8)0x02) /* Alarm Interrupt Enable */
3929 #define RTC_CRH_OWIE ((u8)0x04) /* OverfloW Interrupt Enable */
3930 
3931 
3932 /******************* Bit definition for RTC_CRL register ********************/
3933 #define RTC_CRL_SECF ((u8)0x01) /* Second Flag */
3934 #define RTC_CRL_ALRF ((u8)0x02) /* Alarm Flag */
3935 #define RTC_CRL_OWF ((u8)0x04) /* OverfloW Flag */
3936 #define RTC_CRL_RSF ((u8)0x08) /* Registers Synchronized Flag */
3937 #define RTC_CRL_CNF ((u8)0x10) /* Configuration Flag */
3938 #define RTC_CRL_RTOFF ((u8)0x20) /* RTC operation OFF */
3939 
3940 
3941 /******************* Bit definition for RTC_PRLH register *******************/
3942 #define RTC_PRLH_PRL ((u16)0x000F) /* RTC Prescaler Reload Value High */
3943 
3944 
3945 /******************* Bit definition for RTC_PRLL register *******************/
3946 #define RTC_PRLL_PRL ((u16)0xFFFF) /* RTC Prescaler Reload Value Low */
3947 
3948 
3949 /******************* Bit definition for RTC_DIVH register *******************/
3950 #define RTC_DIVH_RTC_DIV ((u16)0x000F) /* RTC Clock Divider High */
3951 
3952 
3953 /******************* Bit definition for RTC_DIVL register *******************/
3954 #define RTC_DIVL_RTC_DIV ((u16)0xFFFF) /* RTC Clock Divider Low */
3955 
3956 
3957 /******************* Bit definition for RTC_CNTH register *******************/
3958 #define RTC_CNTH_RTC_CNT ((u16)0xFFFF) /* RTC Counter High */
3959 
3960 
3961 /******************* Bit definition for RTC_CNTL register *******************/
3962 #define RTC_CNTL_RTC_CNT ((u16)0xFFFF) /* RTC Counter Low */
3963 
3964 
3965 /******************* Bit definition for RTC_ALRH register *******************/
3966 #define RTC_ALRH_RTC_ALR ((u16)0xFFFF) /* RTC Alarm High */
3967 
3968 
3969 /******************* Bit definition for RTC_ALRL register *******************/
3970 #define RTC_ALRL_RTC_ALR ((u16)0xFFFF) /* RTC Alarm Low */
3971 
3972 
3973 
3974 /******************************************************************************/
3975 /* */
3976 /* Independent WATCHDOG */
3977 /* */
3978 /******************************************************************************/
3979 
3980 /******************* Bit definition for IWDG_KR register ********************/
3981 #define IWDG_KR_KEY ((u16)0xFFFF) /* Key value (write only, read 0000h) */
3982 
3983 
3984 /******************* Bit definition for IWDG_PR register ********************/
3985 #define IWDG_PR_PR ((u8)0x07) /* PR[2:0] (Prescaler divider) */
3986 #define IWDG_PR_PR_0 ((u8)0x01) /* Bit 0 */
3987 #define IWDG_PR_PR_1 ((u8)0x02) /* Bit 1 */
3988 #define IWDG_PR_PR_2 ((u8)0x04) /* Bit 2 */
3989 
3990 
3991 /******************* Bit definition for IWDG_RLR register *******************/
3992 #define IWDG_RLR_RL ((u16)0x0FFF) /* Watchdog counter reload value */
3993 
3994 
3995 /******************* Bit definition for IWDG_SR register ********************/
3996 #define IWDG_SR_PVU ((u8)0x01) /* Watchdog prescaler value update */
3997 #define IWDG_SR_RVU ((u8)0x02) /* Watchdog counter reload value update */
3998 
3999 
4000 
4001 /******************************************************************************/
4002 /* */
4003 /* Window WATCHDOG */
4004 /* */
4005 /******************************************************************************/
4006 
4007 /******************* Bit definition for WWDG_CR register ********************/
4008 #define WWDG_CR_T ((u8)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */
4009 #define WWDG_CR_T0 ((u8)0x01) /* Bit 0 */
4010 #define WWDG_CR_T1 ((u8)0x02) /* Bit 1 */
4011 #define WWDG_CR_T2 ((u8)0x04) /* Bit 2 */
4012 #define WWDG_CR_T3 ((u8)0x08) /* Bit 3 */
4013 #define WWDG_CR_T4 ((u8)0x10) /* Bit 4 */
4014 #define WWDG_CR_T5 ((u8)0x20) /* Bit 5 */
4015 #define WWDG_CR_T6 ((u8)0x40) /* Bit 6 */
4016 
4017 #define WWDG_CR_WDGA ((u8)0x80) /* Activation bit */
4018 
4019 
4020 /******************* Bit definition for WWDG_CFR register *******************/
4021 #define WWDG_CFR_W ((u16)0x007F) /* W[6:0] bits (7-bit window value) */
4022 #define WWDG_CFR_W0 ((u16)0x0001) /* Bit 0 */
4023 #define WWDG_CFR_W1 ((u16)0x0002) /* Bit 1 */
4024 #define WWDG_CFR_W2 ((u16)0x0004) /* Bit 2 */
4025 #define WWDG_CFR_W3 ((u16)0x0008) /* Bit 3 */
4026 #define WWDG_CFR_W4 ((u16)0x0010) /* Bit 4 */
4027 #define WWDG_CFR_W5 ((u16)0x0020) /* Bit 5 */
4028 #define WWDG_CFR_W6 ((u16)0x0040) /* Bit 6 */
4029 
4030 #define WWDG_CFR_WDGTB ((u16)0x0180) /* WDGTB[1:0] bits (Timer Base) */
4031 #define WWDG_CFR_WDGTB0 ((u16)0x0080) /* Bit 0 */
4032 #define WWDG_CFR_WDGTB1 ((u16)0x0100) /* Bit 1 */
4033 
4034 #define WWDG_CFR_EWI ((u16)0x0200) /* Early Wakeup Interrupt */
4035 
4036 
4037 /******************* Bit definition for WWDG_SR register ********************/
4038 #define WWDG_SR_EWIF ((u8)0x01) /* Early Wakeup Interrupt Flag */
4039 
4040 
4041 
4042 /******************************************************************************/
4043 /* */
4044 /* Flexible Static Memory Controller */
4045 /* */
4046 /******************************************************************************/
4047 
4048 /****************** Bit definition for FSMC_BCR1 register *******************/
4049 #define FSMC_BCR1_MBKEN ((u32)0x00000001) /* Memory bank enable bit */
4050 #define FSMC_BCR1_MUXEN ((u32)0x00000002) /* Address/data multiplexing enable bit */
4051 
4052 #define FSMC_BCR1_MTYP ((u32)0x0000000C) /* MTYP[1:0] bits (Memory type) */
4053 #define FSMC_BCR1_MTYP_0 ((u32)0x00000004) /* Bit 0 */
4054 #define FSMC_BCR1_MTYP_1 ((u32)0x00000008) /* Bit 1 */
4055 
4056 #define FSMC_BCR1_MWID ((u32)0x00000030) /* MWID[1:0] bits (Memory data bus width) */
4057 #define FSMC_BCR1_MWID_0 ((u32)0x00000010) /* Bit 0 */
4058 #define FSMC_BCR1_MWID_1 ((u32)0x00000020) /* Bit 1 */
4059 
4060 #define FSMC_BCR1_FACCEN ((u32)0x00000040) /* Flash access enable */
4061 #define FSMC_BCR1_BURSTEN ((u32)0x00000100) /* Burst enable bit */
4062 #define FSMC_BCR1_WAITPOL ((u32)0x00000200) /* Wait signal polarity bit */
4063 #define FSMC_BCR1_WRAPMOD ((u32)0x00000400) /* Wrapped burst mode support */
4064 #define FSMC_BCR1_WAITCFG ((u32)0x00000800) /* Wait timing configuration */
4065 #define FSMC_BCR1_WREN ((u32)0x00001000) /* Write enable bit */
4066 #define FSMC_BCR1_WAITEN ((u32)0x00002000) /* Wait enable bit */
4067 #define FSMC_BCR1_EXTMOD ((u32)0x00004000) /* Extended mode enable */
4068 #define FSMC_BCR1_CBURSTRW ((u32)0x00080000) /* Write burst enable */
4069 
4070 
4071 /****************** Bit definition for FSMC_BCR2 register *******************/
4072 #define FSMC_BCR2_MBKEN ((u32)0x00000001) /* Memory bank enable bit */
4073 #define FSMC_BCR2_MUXEN ((u32)0x00000002) /* Address/data multiplexing enable bit */
4074 
4075 #define FSMC_BCR2_MTYP ((u32)0x0000000C) /* MTYP[1:0] bits (Memory type) */
4076 #define FSMC_BCR2_MTYP_0 ((u32)0x00000004) /* Bit 0 */
4077 #define FSMC_BCR2_MTYP_1 ((u32)0x00000008) /* Bit 1 */
4078 
4079 #define FSMC_BCR2_MWID ((u32)0x00000030) /* MWID[1:0] bits (Memory data bus width) */
4080 #define FSMC_BCR2_MWID_0 ((u32)0x00000010) /* Bit 0 */
4081 #define FSMC_BCR2_MWID_1 ((u32)0x00000020) /* Bit 1 */
4082 
4083 #define FSMC_BCR2_FACCEN ((u32)0x00000040) /* Flash access enable */
4084 #define FSMC_BCR2_BURSTEN ((u32)0x00000100) /* Burst enable bit */
4085 #define FSMC_BCR2_WAITPOL ((u32)0x00000200) /* Wait signal polarity bit */
4086 #define FSMC_BCR2_WRAPMOD ((u32)0x00000400) /* Wrapped burst mode support */
4087 #define FSMC_BCR2_WAITCFG ((u32)0x00000800) /* Wait timing configuration */
4088 #define FSMC_BCR2_WREN ((u32)0x00001000) /* Write enable bit */
4089 #define FSMC_BCR2_WAITEN ((u32)0x00002000) /* Wait enable bit */
4090 #define FSMC_BCR2_EXTMOD ((u32)0x00004000) /* Extended mode enable */
4091 #define FSMC_BCR2_CBURSTRW ((u32)0x00080000) /* Write burst enable */
4092 
4093 
4094 /****************** Bit definition for FSMC_BCR3 register *******************/
4095 #define FSMC_BCR3_MBKEN ((u32)0x00000001) /* Memory bank enable bit */
4096 #define FSMC_BCR3_MUXEN ((u32)0x00000002) /* Address/data multiplexing enable bit */
4097 
4098 #define FSMC_BCR3_MTYP ((u32)0x0000000C) /* MTYP[1:0] bits (Memory type) */
4099 #define FSMC_BCR3_MTYP_0 ((u32)0x00000004) /* Bit 0 */
4100 #define FSMC_BCR3_MTYP_1 ((u32)0x00000008) /* Bit 1 */
4101 
4102 #define FSMC_BCR3_MWID ((u32)0x00000030) /* MWID[1:0] bits (Memory data bus width) */
4103 #define FSMC_BCR3_MWID_0 ((u32)0x00000010) /* Bit 0 */
4104 #define FSMC_BCR3_MWID_1 ((u32)0x00000020) /* Bit 1 */
4105 
4106 #define FSMC_BCR3_FACCEN ((u32)0x00000040) /* Flash access enable */
4107 #define FSMC_BCR3_BURSTEN ((u32)0x00000100) /* Burst enable bit */
4108 #define FSMC_BCR3_WAITPOL ((u32)0x00000200) /* Wait signal polarity bit. */
4109 #define FSMC_BCR3_WRAPMOD ((u32)0x00000400) /* Wrapped burst mode support */
4110 #define FSMC_BCR3_WAITCFG ((u32)0x00000800) /* Wait timing configuration */
4111 #define FSMC_BCR3_WREN ((u32)0x00001000) /* Write enable bit */
4112 #define FSMC_BCR3_WAITEN ((u32)0x00002000) /* Wait enable bit */
4113 #define FSMC_BCR3_EXTMOD ((u32)0x00004000) /* Extended mode enable */
4114 #define FSMC_BCR3_CBURSTRW ((u32)0x00080000) /* Write burst enable */
4115 
4116 
4117 /****************** Bit definition for FSMC_BCR4 register *******************/
4118 #define FSMC_BCR4_MBKEN ((u32)0x00000001) /* Memory bank enable bit */
4119 #define FSMC_BCR4_MUXEN ((u32)0x00000002) /* Address/data multiplexing enable bit */
4120 
4121 #define FSMC_BCR4_MTYP ((u32)0x0000000C) /* MTYP[1:0] bits (Memory type) */
4122 #define FSMC_BCR4_MTYP_0 ((u32)0x00000004) /* Bit 0 */
4123 #define FSMC_BCR4_MTYP_1 ((u32)0x00000008) /* Bit 1 */
4124 
4125 #define FSMC_BCR4_MWID ((u32)0x00000030) /* MWID[1:0] bits (Memory data bus width) */
4126 #define FSMC_BCR4_MWID_0 ((u32)0x00000010) /* Bit 0 */
4127 #define FSMC_BCR4_MWID_1 ((u32)0x00000020) /* Bit 1 */
4128 
4129 #define FSMC_BCR4_FACCEN ((u32)0x00000040) /* Flash access enable */
4130 #define FSMC_BCR4_BURSTEN ((u32)0x00000100) /* Burst enable bit */
4131 #define FSMC_BCR4_WAITPOL ((u32)0x00000200) /* Wait signal polarity bit */
4132 #define FSMC_BCR4_WRAPMOD ((u32)0x00000400) /* Wrapped burst mode support */
4133 #define FSMC_BCR4_WAITCFG ((u32)0x00000800) /* Wait timing configuration */
4134 #define FSMC_BCR4_WREN ((u32)0x00001000) /* Write enable bit */
4135 #define FSMC_BCR4_WAITEN ((u32)0x00002000) /* Wait enable bit */
4136 #define FSMC_BCR4_EXTMOD ((u32)0x00004000) /* Extended mode enable */
4137 #define FSMC_BCR4_CBURSTRW ((u32)0x00080000) /* Write burst enable */
4138 
4139 
4140 /****************** Bit definition for FSMC_BTR1 register ******************/
4141 #define FSMC_BTR1_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */
4142 #define FSMC_BTR1_ADDSET_0 ((u32)0x00000001) /* Bit 0 */
4143 #define FSMC_BTR1_ADDSET_1 ((u32)0x00000002) /* Bit 1 */
4144 #define FSMC_BTR1_ADDSET_2 ((u32)0x00000004) /* Bit 2 */
4145 #define FSMC_BTR1_ADDSET_3 ((u32)0x00000008) /* Bit 3 */
4146 
4147 #define FSMC_BTR1_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */
4148 #define FSMC_BTR1_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */
4149 #define FSMC_BTR1_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */
4150 #define FSMC_BTR1_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */
4151 #define FSMC_BTR1_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */
4152 
4153 #define FSMC_BTR1_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */
4154 #define FSMC_BTR1_DATAST_0 ((u32)0x00000100) /* Bit 0 */
4155 #define FSMC_BTR1_DATAST_1 ((u32)0x00000200) /* Bit 1 */
4156 #define FSMC_BTR1_DATAST_2 ((u32)0x00000400) /* Bit 2 */
4157 #define FSMC_BTR1_DATAST_3 ((u32)0x00000800) /* Bit 3 */
4158 
4159 #define FSMC_BTR1_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */
4160 #define FSMC_BTR1_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */
4161 #define FSMC_BTR1_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */
4162 #define FSMC_BTR1_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */
4163 #define FSMC_BTR1_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */
4164 
4165 #define FSMC_BTR1_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */
4166 #define FSMC_BTR1_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */
4167 #define FSMC_BTR1_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */
4168 #define FSMC_BTR1_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */
4169 #define FSMC_BTR1_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */
4170 
4171 #define FSMC_BTR1_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */
4172 #define FSMC_BTR1_DATLAT_0 ((u32)0x01000000) /* Bit 0 */
4173 #define FSMC_BTR1_DATLAT_1 ((u32)0x02000000) /* Bit 1 */
4174 #define FSMC_BTR1_DATLAT_2 ((u32)0x04000000) /* Bit 2 */
4175 #define FSMC_BTR1_DATLAT_3 ((u32)0x08000000) /* Bit 3 */
4176 
4177 #define FSMC_BTR1_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */
4178 #define FSMC_BTR1_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */
4179 #define FSMC_BTR1_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */
4180 
4181 
4182 /****************** Bit definition for FSMC_BTR2 register *******************/
4183 #define FSMC_BTR2_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */
4184 #define FSMC_BTR2_ADDSET_0 ((u32)0x00000001) /* Bit 0 */
4185 #define FSMC_BTR2_ADDSET_1 ((u32)0x00000002) /* Bit 1 */
4186 #define FSMC_BTR2_ADDSET_2 ((u32)0x00000004) /* Bit 2 */
4187 #define FSMC_BTR2_ADDSET_3 ((u32)0x00000008) /* Bit 3 */
4188 
4189 #define FSMC_BTR2_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */
4190 #define FSMC_BTR2_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */
4191 #define FSMC_BTR2_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */
4192 #define FSMC_BTR2_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */
4193 #define FSMC_BTR2_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */
4194 
4195 #define FSMC_BTR2_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */
4196 #define FSMC_BTR2_DATAST_0 ((u32)0x00000100) /* Bit 0 */
4197 #define FSMC_BTR2_DATAST_1 ((u32)0x00000200) /* Bit 1 */
4198 #define FSMC_BTR2_DATAST_2 ((u32)0x00000400) /* Bit 2 */
4199 #define FSMC_BTR2_DATAST_3 ((u32)0x00000800) /* Bit 3 */
4200 
4201 #define FSMC_BTR2_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */
4202 #define FSMC_BTR2_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */
4203 #define FSMC_BTR2_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */
4204 #define FSMC_BTR2_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */
4205 #define FSMC_BTR2_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */
4206 
4207 #define FSMC_BTR2_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */
4208 #define FSMC_BTR2_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */
4209 #define FSMC_BTR2_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */
4210 #define FSMC_BTR2_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */
4211 #define FSMC_BTR2_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */
4212 
4213 #define FSMC_BTR2_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */
4214 #define FSMC_BTR2_DATLAT_0 ((u32)0x01000000) /* Bit 0 */
4215 #define FSMC_BTR2_DATLAT_1 ((u32)0x02000000) /* Bit 1 */
4216 #define FSMC_BTR2_DATLAT_2 ((u32)0x04000000) /* Bit 2 */
4217 #define FSMC_BTR2_DATLAT_3 ((u32)0x08000000) /* Bit 3 */
4218 
4219 #define FSMC_BTR2_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */
4220 #define FSMC_BTR2_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */
4221 #define FSMC_BTR2_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */
4222 
4223 
4224 /******************* Bit definition for FSMC_BTR3 register *******************/
4225 #define FSMC_BTR3_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */
4226 #define FSMC_BTR3_ADDSET_0 ((u32)0x00000001) /* Bit 0 */
4227 #define FSMC_BTR3_ADDSET_1 ((u32)0x00000002) /* Bit 1 */
4228 #define FSMC_BTR3_ADDSET_2 ((u32)0x00000004) /* Bit 2 */
4229 #define FSMC_BTR3_ADDSET_3 ((u32)0x00000008) /* Bit 3 */
4230 
4231 #define FSMC_BTR3_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */
4232 #define FSMC_BTR3_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */
4233 #define FSMC_BTR3_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */
4234 #define FSMC_BTR3_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */
4235 #define FSMC_BTR3_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */
4236 
4237 #define FSMC_BTR3_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */
4238 #define FSMC_BTR3_DATAST_0 ((u32)0x00000100) /* Bit 0 */
4239 #define FSMC_BTR3_DATAST_1 ((u32)0x00000200) /* Bit 1 */
4240 #define FSMC_BTR3_DATAST_2 ((u32)0x00000400) /* Bit 2 */
4241 #define FSMC_BTR3_DATAST_3 ((u32)0x00000800) /* Bit 3 */
4242 
4243 #define FSMC_BTR3_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */
4244 #define FSMC_BTR3_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */
4245 #define FSMC_BTR3_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */
4246 #define FSMC_BTR3_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */
4247 #define FSMC_BTR3_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */
4248 
4249 #define FSMC_BTR3_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */
4250 #define FSMC_BTR3_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */
4251 #define FSMC_BTR3_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */
4252 #define FSMC_BTR3_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */
4253 #define FSMC_BTR3_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */
4254 
4255 #define FSMC_BTR3_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */
4256 #define FSMC_BTR3_DATLAT_0 ((u32)0x01000000) /* Bit 0 */
4257 #define FSMC_BTR3_DATLAT_1 ((u32)0x02000000) /* Bit 1 */
4258 #define FSMC_BTR3_DATLAT_2 ((u32)0x04000000) /* Bit 2 */
4259 #define FSMC_BTR3_DATLAT_3 ((u32)0x08000000) /* Bit 3 */
4260 
4261 #define FSMC_BTR3_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */
4262 #define FSMC_BTR3_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */
4263 #define FSMC_BTR3_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */
4264 
4265 
4266 /****************** Bit definition for FSMC_BTR4 register *******************/
4267 #define FSMC_BTR4_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */
4268 #define FSMC_BTR4_ADDSET_0 ((u32)0x00000001) /* Bit 0 */
4269 #define FSMC_BTR4_ADDSET_1 ((u32)0x00000002) /* Bit 1 */
4270 #define FSMC_BTR4_ADDSET_2 ((u32)0x00000004) /* Bit 2 */
4271 #define FSMC_BTR4_ADDSET_3 ((u32)0x00000008) /* Bit 3 */
4272 
4273 #define FSMC_BTR4_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */
4274 #define FSMC_BTR4_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */
4275 #define FSMC_BTR4_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */
4276 #define FSMC_BTR4_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */
4277 #define FSMC_BTR4_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */
4278 
4279 #define FSMC_BTR4_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */
4280 #define FSMC_BTR4_DATAST_0 ((u32)0x00000100) /* Bit 0 */
4281 #define FSMC_BTR4_DATAST_1 ((u32)0x00000200) /* Bit 1 */
4282 #define FSMC_BTR4_DATAST_2 ((u32)0x00000400) /* Bit 2 */
4283 #define FSMC_BTR4_DATAST_3 ((u32)0x00000800) /* Bit 3 */
4284 
4285 #define FSMC_BTR4_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */
4286 #define FSMC_BTR4_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */
4287 #define FSMC_BTR4_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */
4288 #define FSMC_BTR4_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */
4289 #define FSMC_BTR4_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */
4290 
4291 #define FSMC_BTR4_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */
4292 #define FSMC_BTR4_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */
4293 #define FSMC_BTR4_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */
4294 #define FSMC_BTR4_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */
4295 #define FSMC_BTR4_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */
4296 
4297 #define FSMC_BTR4_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */
4298 #define FSMC_BTR4_DATLAT_0 ((u32)0x01000000) /* Bit 0 */
4299 #define FSMC_BTR4_DATLAT_1 ((u32)0x02000000) /* Bit 1 */
4300 #define FSMC_BTR4_DATLAT_2 ((u32)0x04000000) /* Bit 2 */
4301 #define FSMC_BTR4_DATLAT_3 ((u32)0x08000000) /* Bit 3 */
4302 
4303 #define FSMC_BTR4_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */
4304 #define FSMC_BTR4_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */
4305 #define FSMC_BTR4_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */
4306 
4307 
4308 /****************** Bit definition for FSMC_BWTR1 register ******************/
4309 #define FSMC_BWTR1_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */
4310 #define FSMC_BWTR1_ADDSET_0 ((u32)0x00000001) /* Bit 0 */
4311 #define FSMC_BWTR1_ADDSET_1 ((u32)0x00000002) /* Bit 1 */
4312 #define FSMC_BWTR1_ADDSET_2 ((u32)0x00000004) /* Bit 2 */
4313 #define FSMC_BWTR1_ADDSET_3 ((u32)0x00000008) /* Bit 3 */
4314 
4315 #define FSMC_BWTR1_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */
4316 #define FSMC_BWTR1_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */
4317 #define FSMC_BWTR1_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */
4318 #define FSMC_BWTR1_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */
4319 #define FSMC_BWTR1_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */
4320 
4321 #define FSMC_BWTR1_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */
4322 #define FSMC_BWTR1_DATAST_0 ((u32)0x00000100) /* Bit 0 */
4323 #define FSMC_BWTR1_DATAST_1 ((u32)0x00000200) /* Bit 1 */
4324 #define FSMC_BWTR1_DATAST_2 ((u32)0x00000400) /* Bit 2 */
4325 #define FSMC_BWTR1_DATAST_3 ((u32)0x00000800) /* Bit 3 */
4326 
4327 #define FSMC_BWTR1_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */
4328 #define FSMC_BWTR1_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */
4329 #define FSMC_BWTR1_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */
4330 #define FSMC_BWTR1_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */
4331 #define FSMC_BWTR1_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */
4332 
4333 #define FSMC_BWTR1_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */
4334 #define FSMC_BWTR1_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */
4335 #define FSMC_BWTR1_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */
4336 #define FSMC_BWTR1_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */
4337 #define FSMC_BWTR1_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */
4338 
4339 #define FSMC_BWTR1_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */
4340 #define FSMC_BWTR1_DATLAT_0 ((u32)0x01000000) /* Bit 0 */
4341 #define FSMC_BWTR1_DATLAT_1 ((u32)0x02000000) /* Bit 1 */
4342 #define FSMC_BWTR1_DATLAT_2 ((u32)0x04000000) /* Bit 2 */
4343 #define FSMC_BWTR1_DATLAT_3 ((u32)0x08000000) /* Bit 3 */
4344 
4345 #define FSMC_BWTR1_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */
4346 #define FSMC_BWTR1_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */
4347 #define FSMC_BWTR1_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */
4348 
4349 
4350 /****************** Bit definition for FSMC_BWTR2 register ******************/
4351 #define FSMC_BWTR2_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */
4352 #define FSMC_BWTR2_ADDSET_0 ((u32)0x00000001) /* Bit 0 */
4353 #define FSMC_BWTR2_ADDSET_1 ((u32)0x00000002) /* Bit 1 */
4354 #define FSMC_BWTR2_ADDSET_2 ((u32)0x00000004) /* Bit 2 */
4355 #define FSMC_BWTR2_ADDSET_3 ((u32)0x00000008) /* Bit 3 */
4356 
4357 #define FSMC_BWTR2_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */
4358 #define FSMC_BWTR2_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */
4359 #define FSMC_BWTR2_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */
4360 #define FSMC_BWTR2_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */
4361 #define FSMC_BWTR2_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */
4362 
4363 #define FSMC_BWTR2_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */
4364 #define FSMC_BWTR2_DATAST_0 ((u32)0x00000100) /* Bit 0 */
4365 #define FSMC_BWTR2_DATAST_1 ((u32)0x00000200) /* Bit 1 */
4366 #define FSMC_BWTR2_DATAST_2 ((u32)0x00000400) /* Bit 2 */
4367 #define FSMC_BWTR2_DATAST_3 ((u32)0x00000800) /* Bit 3 */
4368 
4369 #define FSMC_BWTR2_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */
4370 #define FSMC_BWTR2_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */
4371 #define FSMC_BWTR2_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */
4372 #define FSMC_BWTR2_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */
4373 #define FSMC_BWTR2_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */
4374 
4375 #define FSMC_BWTR2_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */
4376 #define FSMC_BWTR2_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */
4377 #define FSMC_BWTR2_CLKDIV_1 ((u32)0x00200000) /* Bit 1*/
4378 #define FSMC_BWTR2_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */
4379 #define FSMC_BWTR2_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */
4380 
4381 #define FSMC_BWTR2_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */
4382 #define FSMC_BWTR2_DATLAT_0 ((u32)0x01000000) /* Bit 0 */
4383 #define FSMC_BWTR2_DATLAT_1 ((u32)0x02000000) /* Bit 1 */
4384 #define FSMC_BWTR2_DATLAT_2 ((u32)0x04000000) /* Bit 2 */
4385 #define FSMC_BWTR2_DATLAT_3 ((u32)0x08000000) /* Bit 3 */
4386 
4387 #define FSMC_BWTR2_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */
4388 #define FSMC_BWTR2_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */
4389 #define FSMC_BWTR2_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */
4390 
4391 
4392 /****************** Bit definition for FSMC_BWTR3 register ******************/
4393 #define FSMC_BWTR3_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */
4394 #define FSMC_BWTR3_ADDSET_0 ((u32)0x00000001) /* Bit 0 */
4395 #define FSMC_BWTR3_ADDSET_1 ((u32)0x00000002) /* Bit 1 */
4396 #define FSMC_BWTR3_ADDSET_2 ((u32)0x00000004) /* Bit 2 */
4397 #define FSMC_BWTR3_ADDSET_3 ((u32)0x00000008) /* Bit 3 */
4398 
4399 #define FSMC_BWTR3_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */
4400 #define FSMC_BWTR3_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */
4401 #define FSMC_BWTR3_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */
4402 #define FSMC_BWTR3_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */
4403 #define FSMC_BWTR3_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */
4404 
4405 #define FSMC_BWTR3_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */
4406 #define FSMC_BWTR3_DATAST_0 ((u32)0x00000100) /* Bit 0 */
4407 #define FSMC_BWTR3_DATAST_1 ((u32)0x00000200) /* Bit 1 */
4408 #define FSMC_BWTR3_DATAST_2 ((u32)0x00000400) /* Bit 2 */
4409 #define FSMC_BWTR3_DATAST_3 ((u32)0x00000800) /* Bit 3 */
4410 
4411 #define FSMC_BWTR3_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */
4412 #define FSMC_BWTR3_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */
4413 #define FSMC_BWTR3_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */
4414 #define FSMC_BWTR3_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */
4415 #define FSMC_BWTR3_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */
4416 
4417 #define FSMC_BWTR3_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */
4418 #define FSMC_BWTR3_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */
4419 #define FSMC_BWTR3_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */
4420 #define FSMC_BWTR3_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */
4421 #define FSMC_BWTR3_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */
4422 
4423 #define FSMC_BWTR3_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */
4424 #define FSMC_BWTR3_DATLAT_0 ((u32)0x01000000) /* Bit 0 */
4425 #define FSMC_BWTR3_DATLAT_1 ((u32)0x02000000) /* Bit 1 */
4426 #define FSMC_BWTR3_DATLAT_2 ((u32)0x04000000) /* Bit 2 */
4427 #define FSMC_BWTR3_DATLAT_3 ((u32)0x08000000) /* Bit 3 */
4428 
4429 #define FSMC_BWTR3_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */
4430 #define FSMC_BWTR3_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */
4431 #define FSMC_BWTR3_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */
4432 
4433 
4434 /****************** Bit definition for FSMC_BWTR4 register ******************/
4435 #define FSMC_BWTR4_ADDSET ((u32)0x0000000F) /* ADDSET[3:0] bits (Address setup phase duration) */
4436 #define FSMC_BWTR4_ADDSET_0 ((u32)0x00000001) /* Bit 0 */
4437 #define FSMC_BWTR4_ADDSET_1 ((u32)0x00000002) /* Bit 1 */
4438 #define FSMC_BWTR4_ADDSET_2 ((u32)0x00000004) /* Bit 2 */
4439 #define FSMC_BWTR4_ADDSET_3 ((u32)0x00000008) /* Bit 3 */
4440 
4441 #define FSMC_BWTR4_ADDHLD ((u32)0x000000F0) /* ADDHLD[3:0] bits (Address-hold phase duration) */
4442 #define FSMC_BWTR4_ADDHLD_0 ((u32)0x00000010) /* Bit 0 */
4443 #define FSMC_BWTR4_ADDHLD_1 ((u32)0x00000020) /* Bit 1 */
4444 #define FSMC_BWTR4_ADDHLD_2 ((u32)0x00000040) /* Bit 2 */
4445 #define FSMC_BWTR4_ADDHLD_3 ((u32)0x00000080) /* Bit 3 */
4446 
4447 #define FSMC_BWTR4_DATAST ((u32)0x0000FF00) /* DATAST [3:0] bits (Data-phase duration) */
4448 #define FSMC_BWTR4_DATAST_0 ((u32)0x00000100) /* Bit 0 */
4449 #define FSMC_BWTR4_DATAST_1 ((u32)0x00000200) /* Bit 1 */
4450 #define FSMC_BWTR4_DATAST_2 ((u32)0x00000400) /* Bit 2 */
4451 #define FSMC_BWTR4_DATAST_3 ((u32)0x00000800) /* Bit 3 */
4452 
4453 #define FSMC_BWTR4_BUSTURN ((u32)0x000F0000) /* BUSTURN[3:0] bits (Bus turnaround phase duration) */
4454 #define FSMC_BWTR4_BUSTURN_0 ((u32)0x00010000) /* Bit 0 */
4455 #define FSMC_BWTR4_BUSTURN_1 ((u32)0x00020000) /* Bit 1 */
4456 #define FSMC_BWTR4_BUSTURN_2 ((u32)0x00040000) /* Bit 2 */
4457 #define FSMC_BWTR4_BUSTURN_3 ((u32)0x00080000) /* Bit 3 */
4458 
4459 #define FSMC_BWTR4_CLKDIV ((u32)0x00F00000) /* CLKDIV[3:0] bits (Clock divide ratio) */
4460 #define FSMC_BWTR4_CLKDIV_0 ((u32)0x00100000) /* Bit 0 */
4461 #define FSMC_BWTR4_CLKDIV_1 ((u32)0x00200000) /* Bit 1 */
4462 #define FSMC_BWTR4_CLKDIV_2 ((u32)0x00400000) /* Bit 2 */
4463 #define FSMC_BWTR4_CLKDIV_3 ((u32)0x00800000) /* Bit 3 */
4464 
4465 #define FSMC_BWTR4_DATLAT ((u32)0x0F000000) /* DATLA[3:0] bits (Data latency) */
4466 #define FSMC_BWTR4_DATLAT_0 ((u32)0x01000000) /* Bit 0 */
4467 #define FSMC_BWTR4_DATLAT_1 ((u32)0x02000000) /* Bit 1 */
4468 #define FSMC_BWTR4_DATLAT_2 ((u32)0x04000000) /* Bit 2 */
4469 #define FSMC_BWTR4_DATLAT_3 ((u32)0x08000000) /* Bit 3 */
4470 
4471 #define FSMC_BWTR4_ACCMOD ((u32)0x30000000) /* ACCMOD[1:0] bits (Access mode) */
4472 #define FSMC_BWTR4_ACCMOD_0 ((u32)0x10000000) /* Bit 0 */
4473 #define FSMC_BWTR4_ACCMOD_1 ((u32)0x20000000) /* Bit 1 */
4474 
4475 
4476 /****************** Bit definition for FSMC_PCR2 register *******************/
4477 #define FSMC_PCR2_PWAITEN ((u32)0x00000002) /* Wait feature enable bit */
4478 #define FSMC_PCR2_PBKEN ((u32)0x00000004) /* PC Card/NAND Flash memory bank enable bit */
4479 #define FSMC_PCR2_PTYP ((u32)0x00000008) /* Memory type */
4480 
4481 #define FSMC_PCR2_PWID ((u32)0x00000030) /* PWID[1:0] bits (NAND Flash databus width) */
4482 #define FSMC_PCR2_PWID_0 ((u32)0x00000010) /* Bit 0 */
4483 #define FSMC_PCR2_PWID_1 ((u32)0x00000020) /* Bit 1 */
4484 
4485 #define FSMC_PCR2_ECCEN ((u32)0x00000040) /* ECC computation logic enable bit */
4486 #define FSMC_PCR2_ADLOW ((u32)0x00000100) /* Address low bit delivery */
4487 
4488 #define FSMC_PCR2_TCLR ((u32)0x00001E00) /* TCLR[3:0] bits (CLE to RE delay) */
4489 #define FSMC_PCR2_TCLR_0 ((u32)0x00000200) /* Bit 0 */
4490 #define FSMC_PCR2_TCLR_1 ((u32)0x00000400) /* Bit 1 */
4491 #define FSMC_PCR2_TCLR_2 ((u32)0x00000800) /* Bit 2 */
4492 #define FSMC_PCR2_TCLR_3 ((u32)0x00001000) /* Bit 3 */
4493 
4494 #define FSMC_PCR2_TAR ((u32)0x0001E000) /* TAR[3:0] bits (ALE to RE delay) */
4495 #define FSMC_PCR2_TAR_0 ((u32)0x00002000) /* Bit 0 */
4496 #define FSMC_PCR2_TAR_1 ((u32)0x00004000) /* Bit 1 */
4497 #define FSMC_PCR2_TAR_2 ((u32)0x00008000) /* Bit 2 */
4498 #define FSMC_PCR2_TAR_3 ((u32)0x00010000) /* Bit 3 */
4499 
4500 #define FSMC_PCR2_ECCPS ((u32)0x000E0000) /* ECCPS[1:0] bits (ECC page size) */
4501 #define FSMC_PCR2_ECCPS_0 ((u32)0x00020000) /* Bit 0 */
4502 #define FSMC_PCR2_ECCPS_1 ((u32)0x00040000) /* Bit 1 */
4503 #define FSMC_PCR2_ECCPS_2 ((u32)0x00080000) /* Bit 2 */
4504 
4505 
4506 /****************** Bit definition for FSMC_PCR3 register *******************/
4507 #define FSMC_PCR3_PWAITEN ((u32)0x00000002) /* Wait feature enable bit */
4508 #define FSMC_PCR3_PBKEN ((u32)0x00000004) /* PC Card/NAND Flash memory bank enable bit */
4509 #define FSMC_PCR3_PTYP ((u32)0x00000008) /* Memory type */
4510 
4511 #define FSMC_PCR3_PWID ((u32)0x00000030) /* PWID[1:0] bits (NAND Flash databus width) */
4512 #define FSMC_PCR3_PWID_0 ((u32)0x00000010) /* Bit 0 */
4513 #define FSMC_PCR3_PWID_1 ((u32)0x00000020) /* Bit 1 */
4514 
4515 #define FSMC_PCR3_ECCEN ((u32)0x00000040) /* ECC computation logic enable bit */
4516 #define FSMC_PCR3_ADLOW ((u32)0x00000100) /* Address low bit delivery */
4517 
4518 #define FSMC_PCR3_TCLR ((u32)0x00001E00) /* TCLR[3:0] bits (CLE to RE delay) */
4519 #define FSMC_PCR3_TCLR_0 ((u32)0x00000200) /* Bit 0 */
4520 #define FSMC_PCR3_TCLR_1 ((u32)0x00000400) /* Bit 1 */
4521 #define FSMC_PCR3_TCLR_2 ((u32)0x00000800) /* Bit 2 */
4522 #define FSMC_PCR3_TCLR_3 ((u32)0x00001000) /* Bit 3 */
4523 
4524 #define FSMC_PCR3_TAR ((u32)0x0001E000) /* TAR[3:0] bits (ALE to RE delay) */
4525 #define FSMC_PCR3_TAR_0 ((u32)0x00002000) /* Bit 0 */
4526 #define FSMC_PCR3_TAR_1 ((u32)0x00004000) /* Bit 1 */
4527 #define FSMC_PCR3_TAR_2 ((u32)0x00008000) /* Bit 2 */
4528 #define FSMC_PCR3_TAR_3 ((u32)0x00010000) /* Bit 3 */
4529 
4530 #define FSMC_PCR3_ECCPS ((u32)0x000E0000) /* ECCPS[2:0] bits (ECC page size) */
4531 #define FSMC_PCR3_ECCPS_0 ((u32)0x00020000) /* Bit 0 */
4532 #define FSMC_PCR3_ECCPS_1 ((u32)0x00040000) /* Bit 1 */
4533 #define FSMC_PCR3_ECCPS_2 ((u32)0x00080000) /* Bit 2 */
4534 
4535 
4536 /****************** Bit definition for FSMC_PCR4 register *******************/
4537 #define FSMC_PCR4_PWAITEN ((u32)0x00000002) /* Wait feature enable bit */
4538 #define FSMC_PCR4_PBKEN ((u32)0x00000004) /* PC Card/NAND Flash memory bank enable bit */
4539 #define FSMC_PCR4_PTYP ((u32)0x00000008) /* Memory type */
4540 
4541 #define FSMC_PCR4_PWID ((u32)0x00000030) /* PWID[1:0] bits (NAND Flash databus width) */
4542 #define FSMC_PCR4_PWID_0 ((u32)0x00000010) /* Bit 0 */
4543 #define FSMC_PCR4_PWID_1 ((u32)0x00000020) /* Bit 1 */
4544 
4545 #define FSMC_PCR4_ECCEN ((u32)0x00000040) /* ECC computation logic enable bit */
4546 #define FSMC_PCR4_ADLOW ((u32)0x00000100) /* Address low bit delivery */
4547 
4548 #define FSMC_PCR4_TCLR ((u32)0x00001E00) /* TCLR[3:0] bits (CLE to RE delay) */
4549 #define FSMC_PCR4_TCLR_0 ((u32)0x00000200) /* Bit 0 */
4550 #define FSMC_PCR4_TCLR_1 ((u32)0x00000400) /* Bit 1 */
4551 #define FSMC_PCR4_TCLR_2 ((u32)0x00000800) /* Bit 2 */
4552 #define FSMC_PCR4_TCLR_3 ((u32)0x00001000) /* Bit 3 */
4553 
4554 #define FSMC_PCR4_TAR ((u32)0x0001E000) /* TAR[3:0] bits (ALE to RE delay) */
4555 #define FSMC_PCR4_TAR_0 ((u32)0x00002000) /* Bit 0 */
4556 #define FSMC_PCR4_TAR_1 ((u32)0x00004000) /* Bit 1 */
4557 #define FSMC_PCR4_TAR_2 ((u32)0x00008000) /* Bit 2 */
4558 #define FSMC_PCR4_TAR_3 ((u32)0x00010000) /* Bit 3 */
4559 
4560 #define FSMC_PCR4_ECCPS ((u32)0x000E0000) /* ECCPS[2:0] bits (ECC page size) */
4561 #define FSMC_PCR4_ECCPS_0 ((u32)0x00020000) /* Bit 0 */
4562 #define FSMC_PCR4_ECCPS_1 ((u32)0x00040000) /* Bit 1 */
4563 #define FSMC_PCR4_ECCPS_2 ((u32)0x00080000) /* Bit 2 */
4564 
4565 
4566 /******************* Bit definition for FSMC_SR2 register *******************/
4567 #define FSMC_SR2_IRS ((u8)0x01) /* Interrupt Rising Edge status */
4568 #define FSMC_SR2_ILS ((u8)0x02) /* Interrupt Level status */
4569 #define FSMC_SR2_IFS ((u8)0x04) /* Interrupt Falling Edge status */
4570 #define FSMC_SR2_IREN ((u8)0x08) /* Interrupt Rising Edge detection Enable bit */
4571 #define FSMC_SR2_ILEN ((u8)0x10) /* Interrupt Level detection Enable bit */
4572 #define FSMC_SR2_IFEN ((u8)0x20) /* Interrupt Falling Edge detection Enable bit */
4573 #define FSMC_SR2_FEMPT ((u8)0x40) /* FIFO empty */
4574 
4575 
4576 /******************* Bit definition for FSMC_SR3 register *******************/
4577 #define FSMC_SR3_IRS ((u8)0x01) /* Interrupt Rising Edge status */
4578 #define FSMC_SR3_ILS ((u8)0x02) /* Interrupt Level status */
4579 #define FSMC_SR3_IFS ((u8)0x04) /* Interrupt Falling Edge status */
4580 #define FSMC_SR3_IREN ((u8)0x08) /* Interrupt Rising Edge detection Enable bit */
4581 #define FSMC_SR3_ILEN ((u8)0x10) /* Interrupt Level detection Enable bit */
4582 #define FSMC_SR3_IFEN ((u8)0x20) /* Interrupt Falling Edge detection Enable bit */
4583 #define FSMC_SR3_FEMPT ((u8)0x40) /* FIFO empty */
4584 
4585 
4586 /******************* Bit definition for FSMC_SR4 register *******************/
4587 #define FSMC_SR4_IRS ((u8)0x01) /* Interrupt Rising Edge status */
4588 #define FSMC_SR4_ILS ((u8)0x02) /* Interrupt Level status */
4589 #define FSMC_SR4_IFS ((u8)0x04) /* Interrupt Falling Edge status */
4590 #define FSMC_SR4_IREN ((u8)0x08) /* Interrupt Rising Edge detection Enable bit */
4591 #define FSMC_SR4_ILEN ((u8)0x10) /* Interrupt Level detection Enable bit */
4592 #define FSMC_SR4_IFEN ((u8)0x20) /* Interrupt Falling Edge detection Enable bit */
4593 #define FSMC_SR4_FEMPT ((u8)0x40) /* FIFO empty */
4594 
4595 
4596 /****************** Bit definition for FSMC_PMEM2 register ******************/
4597 #define FSMC_PMEM2_MEMSET2 ((u32)0x000000FF) /* MEMSET2[7:0] bits (Common memory 2 setup time) */
4598 #define FSMC_PMEM2_MEMSET2_0 ((u32)0x00000001) /* Bit 0 */
4599 #define FSMC_PMEM2_MEMSET2_1 ((u32)0x00000002) /* Bit 1 */
4600 #define FSMC_PMEM2_MEMSET2_2 ((u32)0x00000004) /* Bit 2 */
4601 #define FSMC_PMEM2_MEMSET2_3 ((u32)0x00000008) /* Bit 3 */
4602 #define FSMC_PMEM2_MEMSET2_4 ((u32)0x00000010) /* Bit 4 */
4603 #define FSMC_PMEM2_MEMSET2_5 ((u32)0x00000020) /* Bit 5 */
4604 #define FSMC_PMEM2_MEMSET2_6 ((u32)0x00000040) /* Bit 6 */
4605 #define FSMC_PMEM2_MEMSET2_7 ((u32)0x00000080) /* Bit 7 */
4606 
4607 #define FSMC_PMEM2_MEMWAIT2 ((u32)0x0000FF00) /* MEMWAIT2[7:0] bits (Common memory 2 wait time) */
4608 #define FSMC_PMEM2_MEMWAIT2_0 ((u32)0x00000100) /* Bit 0 */
4609 #define FSMC_PMEM2_MEMWAIT2_1 ((u32)0x00000200) /* Bit 1 */
4610 #define FSMC_PMEM2_MEMWAIT2_2 ((u32)0x00000400) /* Bit 2 */
4611 #define FSMC_PMEM2_MEMWAIT2_3 ((u32)0x00000800) /* Bit 3 */
4612 #define FSMC_PMEM2_MEMWAIT2_4 ((u32)0x00001000) /* Bit 4 */
4613 #define FSMC_PMEM2_MEMWAIT2_5 ((u32)0x00002000) /* Bit 5 */
4614 #define FSMC_PMEM2_MEMWAIT2_6 ((u32)0x00004000) /* Bit 6 */
4615 #define FSMC_PMEM2_MEMWAIT2_7 ((u32)0x00008000) /* Bit 7 */
4616 
4617 #define FSMC_PMEM2_MEMHOLD2 ((u32)0x00FF0000) /* MEMHOLD2[7:0] bits (Common memory 2 hold time) */
4618 #define FSMC_PMEM2_MEMHOLD2_0 ((u32)0x00010000) /* Bit 0 */
4619 #define FSMC_PMEM2_MEMHOLD2_1 ((u32)0x00020000) /* Bit 1 */
4620 #define FSMC_PMEM2_MEMHOLD2_2 ((u32)0x00040000) /* Bit 2 */
4621 #define FSMC_PMEM2_MEMHOLD2_3 ((u32)0x00080000) /* Bit 3 */
4622 #define FSMC_PMEM2_MEMHOLD2_4 ((u32)0x00100000) /* Bit 4 */
4623 #define FSMC_PMEM2_MEMHOLD2_5 ((u32)0x00200000) /* Bit 5 */
4624 #define FSMC_PMEM2_MEMHOLD2_6 ((u32)0x00400000) /* Bit 6 */
4625 #define FSMC_PMEM2_MEMHOLD2_7 ((u32)0x00800000) /* Bit 7 */
4626 
4627 #define FSMC_PMEM2_MEMHIZ2 ((u32)0xFF000000) /* MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
4628 #define FSMC_PMEM2_MEMHIZ2_0 ((u32)0x01000000) /* Bit 0 */
4629 #define FSMC_PMEM2_MEMHIZ2_1 ((u32)0x02000000) /* Bit 1 */
4630 #define FSMC_PMEM2_MEMHIZ2_2 ((u32)0x04000000) /* Bit 2 */
4631 #define FSMC_PMEM2_MEMHIZ2_3 ((u32)0x08000000) /* Bit 3 */
4632 #define FSMC_PMEM2_MEMHIZ2_4 ((u32)0x10000000) /* Bit 4 */
4633 #define FSMC_PMEM2_MEMHIZ2_5 ((u32)0x20000000) /* Bit 5 */
4634 #define FSMC_PMEM2_MEMHIZ2_6 ((u32)0x40000000) /* Bit 6 */
4635 #define FSMC_PMEM2_MEMHIZ2_7 ((u32)0x80000000) /* Bit 7 */
4636 
4637 
4638 /****************** Bit definition for FSMC_PMEM3 register ******************/
4639 #define FSMC_PMEM3_MEMSET3 ((u32)0x000000FF) /* MEMSET3[7:0] bits (Common memory 3 setup time) */
4640 #define FSMC_PMEM3_MEMSET3_0 ((u32)0x00000001) /* Bit 0 */
4641 #define FSMC_PMEM3_MEMSET3_1 ((u32)0x00000002) /* Bit 1 */
4642 #define FSMC_PMEM3_MEMSET3_2 ((u32)0x00000004) /* Bit 2 */
4643 #define FSMC_PMEM3_MEMSET3_3 ((u32)0x00000008) /* Bit 3 */
4644 #define FSMC_PMEM3_MEMSET3_4 ((u32)0x00000010) /* Bit 4 */
4645 #define FSMC_PMEM3_MEMSET3_5 ((u32)0x00000020) /* Bit 5 */
4646 #define FSMC_PMEM3_MEMSET3_6 ((u32)0x00000040) /* Bit 6 */
4647 #define FSMC_PMEM3_MEMSET3_7 ((u32)0x00000080) /* Bit 7 */
4648 
4649 #define FSMC_PMEM3_MEMWAIT3 ((u32)0x0000FF00) /* MEMWAIT3[7:0] bits (Common memory 3 wait time) */
4650 #define FSMC_PMEM3_MEMWAIT3_0 ((u32)0x00000100) /* Bit 0 */
4651 #define FSMC_PMEM3_MEMWAIT3_1 ((u32)0x00000200) /* Bit 1 */
4652 #define FSMC_PMEM3_MEMWAIT3_2 ((u32)0x00000400) /* Bit 2 */
4653 #define FSMC_PMEM3_MEMWAIT3_3 ((u32)0x00000800) /* Bit 3 */
4654 #define FSMC_PMEM3_MEMWAIT3_4 ((u32)0x00001000) /* Bit 4 */
4655 #define FSMC_PMEM3_MEMWAIT3_5 ((u32)0x00002000) /* Bit 5 */
4656 #define FSMC_PMEM3_MEMWAIT3_6 ((u32)0x00004000) /* Bit 6 */
4657 #define FSMC_PMEM3_MEMWAIT3_7 ((u32)0x00008000) /* Bit 7 */
4658 
4659 #define FSMC_PMEM3_MEMHOLD3 ((u32)0x00FF0000) /* MEMHOLD3[7:0] bits (Common memory 3 hold time) */
4660 #define FSMC_PMEM3_MEMHOLD3_0 ((u32)0x00010000) /* Bit 0 */
4661 #define FSMC_PMEM3_MEMHOLD3_1 ((u32)0x00020000) /* Bit 1 */
4662 #define FSMC_PMEM3_MEMHOLD3_2 ((u32)0x00040000) /* Bit 2 */
4663 #define FSMC_PMEM3_MEMHOLD3_3 ((u32)0x00080000) /* Bit 3 */
4664 #define FSMC_PMEM3_MEMHOLD3_4 ((u32)0x00100000) /* Bit 4 */
4665 #define FSMC_PMEM3_MEMHOLD3_5 ((u32)0x00200000) /* Bit 5 */
4666 #define FSMC_PMEM3_MEMHOLD3_6 ((u32)0x00400000) /* Bit 6 */
4667 #define FSMC_PMEM3_MEMHOLD3_7 ((u32)0x00800000) /* Bit 7 */
4668 
4669 #define FSMC_PMEM3_MEMHIZ3 ((u32)0xFF000000) /* MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
4670 #define FSMC_PMEM3_MEMHIZ3_0 ((u32)0x01000000) /* Bit 0 */
4671 #define FSMC_PMEM3_MEMHIZ3_1 ((u32)0x02000000) /* Bit 1 */
4672 #define FSMC_PMEM3_MEMHIZ3_2 ((u32)0x04000000) /* Bit 2 */
4673 #define FSMC_PMEM3_MEMHIZ3_3 ((u32)0x08000000) /* Bit 3 */
4674 #define FSMC_PMEM3_MEMHIZ3_4 ((u32)0x10000000) /* Bit 4 */
4675 #define FSMC_PMEM3_MEMHIZ3_5 ((u32)0x20000000) /* Bit 5 */
4676 #define FSMC_PMEM3_MEMHIZ3_6 ((u32)0x40000000) /* Bit 6 */
4677 #define FSMC_PMEM3_MEMHIZ3_7 ((u32)0x80000000) /* Bit 7 */
4678 
4679 
4680 /****************** Bit definition for FSMC_PMEM4 register ******************/
4681 #define FSMC_PMEM4_MEMSET4 ((u32)0x000000FF) /* MEMSET4[7:0] bits (Common memory 4 setup time) */
4682 #define FSMC_PMEM4_MEMSET4_0 ((u32)0x00000001) /* Bit 0 */
4683 #define FSMC_PMEM4_MEMSET4_1 ((u32)0x00000002) /* Bit 1 */
4684 #define FSMC_PMEM4_MEMSET4_2 ((u32)0x00000004) /* Bit 2 */
4685 #define FSMC_PMEM4_MEMSET4_3 ((u32)0x00000008) /* Bit 3 */
4686 #define FSMC_PMEM4_MEMSET4_4 ((u32)0x00000010) /* Bit 4 */
4687 #define FSMC_PMEM4_MEMSET4_5 ((u32)0x00000020) /* Bit 5 */
4688 #define FSMC_PMEM4_MEMSET4_6 ((u32)0x00000040) /* Bit 6 */
4689 #define FSMC_PMEM4_MEMSET4_7 ((u32)0x00000080) /* Bit 7 */
4690 
4691 #define FSMC_PMEM4_MEMWAIT4 ((u32)0x0000FF00) /* MEMWAIT4[7:0] bits (Common memory 4 wait time) */
4692 #define FSMC_PMEM4_MEMWAIT4_0 ((u32)0x00000100) /* Bit 0 */
4693 #define FSMC_PMEM4_MEMWAIT4_1 ((u32)0x00000200) /* Bit 1 */
4694 #define FSMC_PMEM4_MEMWAIT4_2 ((u32)0x00000400) /* Bit 2 */
4695 #define FSMC_PMEM4_MEMWAIT4_3 ((u32)0x00000800) /* Bit 3 */
4696 #define FSMC_PMEM4_MEMWAIT4_4 ((u32)0x00001000) /* Bit 4 */
4697 #define FSMC_PMEM4_MEMWAIT4_5 ((u32)0x00002000) /* Bit 5 */
4698 #define FSMC_PMEM4_MEMWAIT4_6 ((u32)0x00004000) /* Bit 6 */
4699 #define FSMC_PMEM4_MEMWAIT4_7 ((u32)0x00008000) /* Bit 7 */
4700 
4701 #define FSMC_PMEM4_MEMHOLD4 ((u32)0x00FF0000) /* MEMHOLD4[7:0] bits (Common memory 4 hold time) */
4702 #define FSMC_PMEM4_MEMHOLD4_0 ((u32)0x00010000) /* Bit 0 */
4703 #define FSMC_PMEM4_MEMHOLD4_1 ((u32)0x00020000) /* Bit 1 */
4704 #define FSMC_PMEM4_MEMHOLD4_2 ((u32)0x00040000) /* Bit 2 */
4705 #define FSMC_PMEM4_MEMHOLD4_3 ((u32)0x00080000) /* Bit 3 */
4706 #define FSMC_PMEM4_MEMHOLD4_4 ((u32)0x00100000) /* Bit 4 */
4707 #define FSMC_PMEM4_MEMHOLD4_5 ((u32)0x00200000) /* Bit 5 */
4708 #define FSMC_PMEM4_MEMHOLD4_6 ((u32)0x00400000) /* Bit 6 */
4709 #define FSMC_PMEM4_MEMHOLD4_7 ((u32)0x00800000) /* Bit 7 */
4710 
4711 #define FSMC_PMEM4_MEMHIZ4 ((u32)0xFF000000) /* MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
4712 #define FSMC_PMEM4_MEMHIZ4_0 ((u32)0x01000000) /* Bit 0 */
4713 #define FSMC_PMEM4_MEMHIZ4_1 ((u32)0x02000000) /* Bit 1 */
4714 #define FSMC_PMEM4_MEMHIZ4_2 ((u32)0x04000000) /* Bit 2 */
4715 #define FSMC_PMEM4_MEMHIZ4_3 ((u32)0x08000000) /* Bit 3 */
4716 #define FSMC_PMEM4_MEMHIZ4_4 ((u32)0x10000000) /* Bit 4 */
4717 #define FSMC_PMEM4_MEMHIZ4_5 ((u32)0x20000000) /* Bit 5 */
4718 #define FSMC_PMEM4_MEMHIZ4_6 ((u32)0x40000000) /* Bit 6 */
4719 #define FSMC_PMEM4_MEMHIZ4_7 ((u32)0x80000000) /* Bit 7 */
4720 
4721 
4722 /****************** Bit definition for FSMC_PATT2 register ******************/
4723 #define FSMC_PATT2_ATTSET2 ((u32)0x000000FF) /* ATTSET2[7:0] bits (Attribute memory 2 setup time) */
4724 #define FSMC_PATT2_ATTSET2_0 ((u32)0x00000001) /* Bit 0 */
4725 #define FSMC_PATT2_ATTSET2_1 ((u32)0x00000002) /* Bit 1 */
4726 #define FSMC_PATT2_ATTSET2_2 ((u32)0x00000004) /* Bit 2 */
4727 #define FSMC_PATT2_ATTSET2_3 ((u32)0x00000008) /* Bit 3 */
4728 #define FSMC_PATT2_ATTSET2_4 ((u32)0x00000010) /* Bit 4 */
4729 #define FSMC_PATT2_ATTSET2_5 ((u32)0x00000020) /* Bit 5 */
4730 #define FSMC_PATT2_ATTSET2_6 ((u32)0x00000040) /* Bit 6 */
4731 #define FSMC_PATT2_ATTSET2_7 ((u32)0x00000080) /* Bit 7 */
4732 
4733 #define FSMC_PATT2_ATTWAIT2 ((u32)0x0000FF00) /* ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
4734 #define FSMC_PATT2_ATTWAIT2_0 ((u32)0x00000100) /* Bit 0 */
4735 #define FSMC_PATT2_ATTWAIT2_1 ((u32)0x00000200) /* Bit 1 */
4736 #define FSMC_PATT2_ATTWAIT2_2 ((u32)0x00000400) /* Bit 2 */
4737 #define FSMC_PATT2_ATTWAIT2_3 ((u32)0x00000800) /* Bit 3 */
4738 #define FSMC_PATT2_ATTWAIT2_4 ((u32)0x00001000) /* Bit 4 */
4739 #define FSMC_PATT2_ATTWAIT2_5 ((u32)0x00002000) /* Bit 5 */
4740 #define FSMC_PATT2_ATTWAIT2_6 ((u32)0x00004000) /* Bit 6 */
4741 #define FSMC_PATT2_ATTWAIT2_7 ((u32)0x00008000) /* Bit 7 */
4742 
4743 #define FSMC_PATT2_ATTHOLD2 ((u32)0x00FF0000) /* ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
4744 #define FSMC_PATT2_ATTHOLD2_0 ((u32)0x00010000) /* Bit 0 */
4745 #define FSMC_PATT2_ATTHOLD2_1 ((u32)0x00020000) /* Bit 1 */
4746 #define FSMC_PATT2_ATTHOLD2_2 ((u32)0x00040000) /* Bit 2 */
4747 #define FSMC_PATT2_ATTHOLD2_3 ((u32)0x00080000) /* Bit 3 */
4748 #define FSMC_PATT2_ATTHOLD2_4 ((u32)0x00100000) /* Bit 4 */
4749 #define FSMC_PATT2_ATTHOLD2_5 ((u32)0x00200000) /* Bit 5 */
4750 #define FSMC_PATT2_ATTHOLD2_6 ((u32)0x00400000) /* Bit 6 */
4751 #define FSMC_PATT2_ATTHOLD2_7 ((u32)0x00800000) /* Bit 7 */
4752 
4753 #define FSMC_PATT2_ATTHIZ2 ((u32)0xFF000000) /* ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
4754 #define FSMC_PATT2_ATTHIZ2_0 ((u32)0x01000000) /* Bit 0 */
4755 #define FSMC_PATT2_ATTHIZ2_1 ((u32)0x02000000) /* Bit 1 */
4756 #define FSMC_PATT2_ATTHIZ2_2 ((u32)0x04000000) /* Bit 2 */
4757 #define FSMC_PATT2_ATTHIZ2_3 ((u32)0x08000000) /* Bit 3 */
4758 #define FSMC_PATT2_ATTHIZ2_4 ((u32)0x10000000) /* Bit 4 */
4759 #define FSMC_PATT2_ATTHIZ2_5 ((u32)0x20000000) /* Bit 5 */
4760 #define FSMC_PATT2_ATTHIZ2_6 ((u32)0x40000000) /* Bit 6 */
4761 #define FSMC_PATT2_ATTHIZ2_7 ((u32)0x80000000) /* Bit 7 */
4762 
4763 
4764 /****************** Bit definition for FSMC_PATT3 register ******************/
4765 #define FSMC_PATT3_ATTSET3 ((u32)0x000000FF) /* ATTSET3[7:0] bits (Attribute memory 3 setup time) */
4766 #define FSMC_PATT3_ATTSET3_0 ((u32)0x00000001) /* Bit 0 */
4767 #define FSMC_PATT3_ATTSET3_1 ((u32)0x00000002) /* Bit 1 */
4768 #define FSMC_PATT3_ATTSET3_2 ((u32)0x00000004) /* Bit 2 */
4769 #define FSMC_PATT3_ATTSET3_3 ((u32)0x00000008) /* Bit 3 */
4770 #define FSMC_PATT3_ATTSET3_4 ((u32)0x00000010) /* Bit 4 */
4771 #define FSMC_PATT3_ATTSET3_5 ((u32)0x00000020) /* Bit 5 */
4772 #define FSMC_PATT3_ATTSET3_6 ((u32)0x00000040) /* Bit 6 */
4773 #define FSMC_PATT3_ATTSET3_7 ((u32)0x00000080) /* Bit 7 */
4774 
4775 #define FSMC_PATT3_ATTWAIT3 ((u32)0x0000FF00) /* ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
4776 #define FSMC_PATT3_ATTWAIT3_0 ((u32)0x00000100) /* Bit 0 */
4777 #define FSMC_PATT3_ATTWAIT3_1 ((u32)0x00000200) /* Bit 1 */
4778 #define FSMC_PATT3_ATTWAIT3_2 ((u32)0x00000400) /* Bit 2 */
4779 #define FSMC_PATT3_ATTWAIT3_3 ((u32)0x00000800) /* Bit 3 */
4780 #define FSMC_PATT3_ATTWAIT3_4 ((u32)0x00001000) /* Bit 4 */
4781 #define FSMC_PATT3_ATTWAIT3_5 ((u32)0x00002000) /* Bit 5 */
4782 #define FSMC_PATT3_ATTWAIT3_6 ((u32)0x00004000) /* Bit 6 */
4783 #define FSMC_PATT3_ATTWAIT3_7 ((u32)0x00008000) /* Bit 7 */
4784 
4785 #define FSMC_PATT3_ATTHOLD3 ((u32)0x00FF0000) /* ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
4786 #define FSMC_PATT3_ATTHOLD3_0 ((u32)0x00010000) /* Bit 0 */
4787 #define FSMC_PATT3_ATTHOLD3_1 ((u32)0x00020000) /* Bit 1 */
4788 #define FSMC_PATT3_ATTHOLD3_2 ((u32)0x00040000) /* Bit 2 */
4789 #define FSMC_PATT3_ATTHOLD3_3 ((u32)0x00080000) /* Bit 3 */
4790 #define FSMC_PATT3_ATTHOLD3_4 ((u32)0x00100000) /* Bit 4 */
4791 #define FSMC_PATT3_ATTHOLD3_5 ((u32)0x00200000) /* Bit 5 */
4792 #define FSMC_PATT3_ATTHOLD3_6 ((u32)0x00400000) /* Bit 6 */
4793 #define FSMC_PATT3_ATTHOLD3_7 ((u32)0x00800000) /* Bit 7 */
4794 
4795 #define FSMC_PATT3_ATTHIZ3 ((u32)0xFF000000) /* ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
4796 #define FSMC_PATT3_ATTHIZ3_0 ((u32)0x01000000) /* Bit 0 */
4797 #define FSMC_PATT3_ATTHIZ3_1 ((u32)0x02000000) /* Bit 1 */
4798 #define FSMC_PATT3_ATTHIZ3_2 ((u32)0x04000000) /* Bit 2 */
4799 #define FSMC_PATT3_ATTHIZ3_3 ((u32)0x08000000) /* Bit 3 */
4800 #define FSMC_PATT3_ATTHIZ3_4 ((u32)0x10000000) /* Bit 4 */
4801 #define FSMC_PATT3_ATTHIZ3_5 ((u32)0x20000000) /* Bit 5 */
4802 #define FSMC_PATT3_ATTHIZ3_6 ((u32)0x40000000) /* Bit 6 */
4803 #define FSMC_PATT3_ATTHIZ3_7 ((u32)0x80000000) /* Bit 7 */
4804 
4805 
4806 /****************** Bit definition for FSMC_PATT4 register ******************/
4807 #define FSMC_PATT4_ATTSET4 ((u32)0x000000FF) /* ATTSET4[7:0] bits (Attribute memory 4 setup time) */
4808 #define FSMC_PATT4_ATTSET4_0 ((u32)0x00000001) /* Bit 0 */
4809 #define FSMC_PATT4_ATTSET4_1 ((u32)0x00000002) /* Bit 1 */
4810 #define FSMC_PATT4_ATTSET4_2 ((u32)0x00000004) /* Bit 2 */
4811 #define FSMC_PATT4_ATTSET4_3 ((u32)0x00000008) /* Bit 3 */
4812 #define FSMC_PATT4_ATTSET4_4 ((u32)0x00000010) /* Bit 4 */
4813 #define FSMC_PATT4_ATTSET4_5 ((u32)0x00000020) /* Bit 5 */
4814 #define FSMC_PATT4_ATTSET4_6 ((u32)0x00000040) /* Bit 6 */
4815 #define FSMC_PATT4_ATTSET4_7 ((u32)0x00000080) /* Bit 7 */
4816 
4817 #define FSMC_PATT4_ATTWAIT4 ((u32)0x0000FF00) /* ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
4818 #define FSMC_PATT4_ATTWAIT4_0 ((u32)0x00000100) /* Bit 0 */
4819 #define FSMC_PATT4_ATTWAIT4_1 ((u32)0x00000200) /* Bit 1 */
4820 #define FSMC_PATT4_ATTWAIT4_2 ((u32)0x00000400) /* Bit 2 */
4821 #define FSMC_PATT4_ATTWAIT4_3 ((u32)0x00000800) /* Bit 3 */
4822 #define FSMC_PATT4_ATTWAIT4_4 ((u32)0x00001000) /* Bit 4 */
4823 #define FSMC_PATT4_ATTWAIT4_5 ((u32)0x00002000) /* Bit 5 */
4824 #define FSMC_PATT4_ATTWAIT4_6 ((u32)0x00004000) /* Bit 6 */
4825 #define FSMC_PATT4_ATTWAIT4_7 ((u32)0x00008000) /* Bit 7 */
4826 
4827 #define FSMC_PATT4_ATTHOLD4 ((u32)0x00FF0000) /* ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
4828 #define FSMC_PATT4_ATTHOLD4_0 ((u32)0x00010000) /* Bit 0 */
4829 #define FSMC_PATT4_ATTHOLD4_1 ((u32)0x00020000) /* Bit 1 */
4830 #define FSMC_PATT4_ATTHOLD4_2 ((u32)0x00040000) /* Bit 2 */
4831 #define FSMC_PATT4_ATTHOLD4_3 ((u32)0x00080000) /* Bit 3 */
4832 #define FSMC_PATT4_ATTHOLD4_4 ((u32)0x00100000) /* Bit 4 */
4833 #define FSMC_PATT4_ATTHOLD4_5 ((u32)0x00200000) /* Bit 5 */
4834 #define FSMC_PATT4_ATTHOLD4_6 ((u32)0x00400000) /* Bit 6 */
4835 #define FSMC_PATT4_ATTHOLD4_7 ((u32)0x00800000) /* Bit 7 */
4836 
4837 #define FSMC_PATT4_ATTHIZ4 ((u32)0xFF000000) /* ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
4838 #define FSMC_PATT4_ATTHIZ4_0 ((u32)0x01000000) /* Bit 0 */
4839 #define FSMC_PATT4_ATTHIZ4_1 ((u32)0x02000000) /* Bit 1 */
4840 #define FSMC_PATT4_ATTHIZ4_2 ((u32)0x04000000) /* Bit 2 */
4841 #define FSMC_PATT4_ATTHIZ4_3 ((u32)0x08000000) /* Bit 3 */
4842 #define FSMC_PATT4_ATTHIZ4_4 ((u32)0x10000000) /* Bit 4 */
4843 #define FSMC_PATT4_ATTHIZ4_5 ((u32)0x20000000) /* Bit 5 */
4844 #define FSMC_PATT4_ATTHIZ4_6 ((u32)0x40000000) /* Bit 6 */
4845 #define FSMC_PATT4_ATTHIZ4_7 ((u32)0x80000000) /* Bit 7 */
4846 
4847 
4848 /****************** Bit definition for FSMC_PIO4 register *******************/
4849 #define FSMC_PIO4_IOSET4 ((u32)0x000000FF) /* IOSET4[7:0] bits (I/O 4 setup time) */
4850 #define FSMC_PIO4_IOSET4_0 ((u32)0x00000001) /* Bit 0 */
4851 #define FSMC_PIO4_IOSET4_1 ((u32)0x00000002) /* Bit 1 */
4852 #define FSMC_PIO4_IOSET4_2 ((u32)0x00000004) /* Bit 2 */
4853 #define FSMC_PIO4_IOSET4_3 ((u32)0x00000008) /* Bit 3 */
4854 #define FSMC_PIO4_IOSET4_4 ((u32)0x00000010) /* Bit 4 */
4855 #define FSMC_PIO4_IOSET4_5 ((u32)0x00000020) /* Bit 5 */
4856 #define FSMC_PIO4_IOSET4_6 ((u32)0x00000040) /* Bit 6 */
4857 #define FSMC_PIO4_IOSET4_7 ((u32)0x00000080) /* Bit 7 */
4858 
4859 #define FSMC_PIO4_IOWAIT4 ((u32)0x0000FF00) /* IOWAIT4[7:0] bits (I/O 4 wait time) */
4860 #define FSMC_PIO4_IOWAIT4_0 ((u32)0x00000100) /* Bit 0 */
4861 #define FSMC_PIO4_IOWAIT4_1 ((u32)0x00000200) /* Bit 1 */
4862 #define FSMC_PIO4_IOWAIT4_2 ((u32)0x00000400) /* Bit 2 */
4863 #define FSMC_PIO4_IOWAIT4_3 ((u32)0x00000800) /* Bit 3 */
4864 #define FSMC_PIO4_IOWAIT4_4 ((u32)0x00001000) /* Bit 4 */
4865 #define FSMC_PIO4_IOWAIT4_5 ((u32)0x00002000) /* Bit 5 */
4866 #define FSMC_PIO4_IOWAIT4_6 ((u32)0x00004000) /* Bit 6 */
4867 #define FSMC_PIO4_IOWAIT4_7 ((u32)0x00008000) /* Bit 7 */
4868 
4869 #define FSMC_PIO4_IOHOLD4 ((u32)0x00FF0000) /* IOHOLD4[7:0] bits (I/O 4 hold time) */
4870 #define FSMC_PIO4_IOHOLD4_0 ((u32)0x00010000) /* Bit 0 */
4871 #define FSMC_PIO4_IOHOLD4_1 ((u32)0x00020000) /* Bit 1 */
4872 #define FSMC_PIO4_IOHOLD4_2 ((u32)0x00040000) /* Bit 2 */
4873 #define FSMC_PIO4_IOHOLD4_3 ((u32)0x00080000) /* Bit 3 */
4874 #define FSMC_PIO4_IOHOLD4_4 ((u32)0x00100000) /* Bit 4 */
4875 #define FSMC_PIO4_IOHOLD4_5 ((u32)0x00200000) /* Bit 5 */
4876 #define FSMC_PIO4_IOHOLD4_6 ((u32)0x00400000) /* Bit 6 */
4877 #define FSMC_PIO4_IOHOLD4_7 ((u32)0x00800000) /* Bit 7 */
4878 
4879 #define FSMC_PIO4_IOHIZ4 ((u32)0xFF000000) /* IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
4880 #define FSMC_PIO4_IOHIZ4_0 ((u32)0x01000000) /* Bit 0 */
4881 #define FSMC_PIO4_IOHIZ4_1 ((u32)0x02000000) /* Bit 1 */
4882 #define FSMC_PIO4_IOHIZ4_2 ((u32)0x04000000) /* Bit 2 */
4883 #define FSMC_PIO4_IOHIZ4_3 ((u32)0x08000000) /* Bit 3 */
4884 #define FSMC_PIO4_IOHIZ4_4 ((u32)0x10000000) /* Bit 4 */
4885 #define FSMC_PIO4_IOHIZ4_5 ((u32)0x20000000) /* Bit 5 */
4886 #define FSMC_PIO4_IOHIZ4_6 ((u32)0x40000000) /* Bit 6 */
4887 #define FSMC_PIO4_IOHIZ4_7 ((u32)0x80000000) /* Bit 7 */
4888 
4889 
4890 /****************** Bit definition for FSMC_ECCR2 register ******************/
4891 #define FSMC_ECCR2_ECC2 ((u32)0xFFFFFFFF) /* ECC result */
4892 
4893 /****************** Bit definition for FSMC_ECCR3 register ******************/
4894 #define FSMC_ECCR3_ECC3 ((u32)0xFFFFFFFF) /* ECC result */
4895 
4896 
4897 
4898 /******************************************************************************/
4899 /* */
4900 /* SD host Interface */
4901 /* */
4902 /******************************************************************************/
4903 
4904 /****************** Bit definition for SDIO_POWER register ******************/
4905 #define SDIO_POWER_PWRCTRL ((u8)0x03) /* PWRCTRL[1:0] bits (Power supply control bits) */
4906 #define SDIO_POWER_PWRCTRL_0 ((u8)0x01) /* Bit 0 */
4907 #define SDIO_POWER_PWRCTRL_1 ((u8)0x02) /* Bit 1 */
4908 
4909 
4910 /****************** Bit definition for SDIO_CLKCR register ******************/
4911 #define SDIO_CLKCR_CLKDIV ((u16)0x00FF) /* Clock divide factor */
4912 #define SDIO_CLKCR_CLKEN ((u16)0x0100) /* Clock enable bit */
4913 #define SDIO_CLKCR_PWRSAV ((u16)0x0200) /* Power saving configuration bit */
4914 #define SDIO_CLKCR_BYPASS ((u16)0x0400) /* Clock divider bypass enable bit */
4915 
4916 #define SDIO_CLKCR_WIDBUS ((u16)0x1800) /* WIDBUS[1:0] bits (Wide bus mode enable bit) */
4917 #define SDIO_CLKCR_WIDBUS_0 ((u16)0x0800) /* Bit 0 */
4918 #define SDIO_CLKCR_WIDBUS_1 ((u16)0x1000) /* Bit 1 */
4919 
4920 #define SDIO_CLKCR_NEGEDGE ((u16)0x2000) /* SDIO_CK dephasing selection bit */
4921 #define SDIO_CLKCR_HWFC_EN ((u16)0x4000) /* HW Flow Control enable */
4922 
4923 
4924 /******************* Bit definition for SDIO_ARG register *******************/
4925 #define SDIO_ARG_CMDARG ((u32)0xFFFFFFFF) /* Command argument */
4926 
4927 
4928 /******************* Bit definition for SDIO_CMD register *******************/
4929 #define SDIO_CMD_CMDINDEX ((u16)0x003F) /* Command Index */
4930 
4931 #define SDIO_CMD_WAITRESP ((u16)0x00C0) /* WAITRESP[1:0] bits (Wait for response bits) */
4932 #define SDIO_CMD_WAITRESP_0 ((u16)0x0040) /* Bit 0 */
4933 #define SDIO_CMD_WAITRESP_1 ((u16)0x0080) /* Bit 1 */
4934 
4935 #define SDIO_CMD_WAITINT ((u16)0x0100) /* CPSM Waits for Interrupt Request */
4936 #define SDIO_CMD_WAITPEND ((u16)0x0200) /* CPSM Waits for ends of data transfer (CmdPend internal signal) */
4937 #define SDIO_CMD_CPSMEN ((u16)0x0400) /* Command path state machine (CPSM) Enable bit */
4938 #define SDIO_CMD_SDIOSUSPEND ((u16)0x0800) /* SD I/O suspend command */
4939 #define SDIO_CMD_ENCMDCOMPL ((u16)0x1000) /* Enable CMD completion */
4940 #define SDIO_CMD_NIEN ((u16)0x2000) /* Not Interrupt Enable */
4941 #define SDIO_CMD_CEATACMD ((u16)0x4000) /* CE-ATA command */
4942 
4943 
4944 /***************** Bit definition for SDIO_RESPCMD register *****************/
4945 #define SDIO_RESPCMD_RESPCMD ((u8)0x3F) /* Response command index */
4946 
4947 
4948 /****************** Bit definition for SDIO_RESP0 register ******************/
4949 #define SDIO_RESP0_CARDSTATUS0 ((u32)0xFFFFFFFF) /* Card Status */
4950 
4951 
4952 /****************** Bit definition for SDIO_RESP1 register ******************/
4953 #define SDIO_RESP1_CARDSTATUS1 ((u32)0xFFFFFFFF) /* Card Status */
4954 
4955 
4956 /****************** Bit definition for SDIO_RESP2 register ******************/
4957 #define SDIO_RESP2_CARDSTATUS2 ((u32)0xFFFFFFFF) /* Card Status */
4958 
4959 
4960 /****************** Bit definition for SDIO_RESP3 register ******************/
4961 #define SDIO_RESP3_CARDSTATUS3 ((u32)0xFFFFFFFF) /* Card Status */
4962 
4963 
4964 /****************** Bit definition for SDIO_RESP4 register ******************/
4965 #define SDIO_RESP4_CARDSTATUS4 ((u32)0xFFFFFFFF) /* Card Status */
4966 
4967 
4968 /****************** Bit definition for SDIO_DTIMER register *****************/
4969 #define SDIO_DTIMER_DATATIME ((u32)0xFFFFFFFF) /* Data timeout period. */
4970 
4971 
4972 /****************** Bit definition for SDIO_DLEN register *******************/
4973 #define SDIO_DLEN_DATALENGTH ((u32)0x01FFFFFF) /* Data length value */
4974 
4975 
4976 /****************** Bit definition for SDIO_DCTRL register ******************/
4977 #define SDIO_DCTRL_DTEN ((u16)0x0001) /* Data transfer enabled bit */
4978 #define SDIO_DCTRL_DTDIR ((u16)0x0002) /* Data transfer direction selection */
4979 #define SDIO_DCTRL_DTMODE ((u16)0x0004) /* Data transfer mode selection */
4980 #define SDIO_DCTRL_DMAEN ((u16)0x0008) /* DMA enabled bit */
4981 
4982 #define SDIO_DCTRL_DBLOCKSIZE ((u16)0x00F0) /* DBLOCKSIZE[3:0] bits (Data block size) */
4983 #define SDIO_DCTRL_DBLOCKSIZE_0 ((u16)0x0010) /* Bit 0 */
4984 #define SDIO_DCTRL_DBLOCKSIZE_1 ((u16)0x0020) /* Bit 1 */
4985 #define SDIO_DCTRL_DBLOCKSIZE_2 ((u16)0x0040) /* Bit 2 */
4986 #define SDIO_DCTRL_DBLOCKSIZE_3 ((u16)0x0080) /* Bit 3 */
4987 
4988 #define SDIO_DCTRL_RWSTART ((u16)0x0100) /* Read wait start */
4989 #define SDIO_DCTRL_RWSTOP ((u16)0x0200) /* Read wait stop */
4990 #define SDIO_DCTRL_RWMOD ((u16)0x0400) /* Read wait mode */
4991 #define SDIO_DCTRL_SDIOEN ((u16)0x0800) /* SD I/O enable functions */
4992 
4993 
4994 /****************** Bit definition for SDIO_DCOUNT register *****************/
4995 #define SDIO_DCOUNT_DATACOUNT ((u32)0x01FFFFFF) /* Data count value */
4996 
4997 
4998 /****************** Bit definition for SDIO_STA register ********************/
4999 #define SDIO_STA_CCRCFAIL ((u32)0x00000001) /* Command response received (CRC check failed) */
5000 #define SDIO_STA_DCRCFAIL ((u32)0x00000002) /* Data block sent/received (CRC check failed) */
5001 #define SDIO_STA_CTIMEOUT ((u32)0x00000004) /* Command response timeout */
5002 #define SDIO_STA_DTIMEOUT ((u32)0x00000008) /* Data timeout */
5003 #define SDIO_STA_TXUNDERR ((u32)0x00000010) /* Transmit FIFO underrun error */
5004 #define SDIO_STA_RXOVERR ((u32)0x00000020) /* Received FIFO overrun error */
5005 #define SDIO_STA_CMDREND ((u32)0x00000040) /* Command response received (CRC check passed) */
5006 #define SDIO_STA_CMDSENT ((u32)0x00000080) /* Command sent (no response required) */
5007 #define SDIO_STA_DATAEND ((u32)0x00000100) /* Data end (data counter, SDIDCOUNT, is zero) */
5008 #define SDIO_STA_STBITERR ((u32)0x00000200) /* Start bit not detected on all data signals in wide bus mode */
5009 #define SDIO_STA_DBCKEND ((u32)0x00000400) /* Data block sent/received (CRC check passed) */
5010 #define SDIO_STA_CMDACT ((u32)0x00000800) /* Command transfer in progress */
5011 #define SDIO_STA_TXACT ((u32)0x00001000) /* Data transmit in progress */
5012 #define SDIO_STA_RXACT ((u32)0x00002000) /* Data receive in progress */
5013 #define SDIO_STA_TXFIFOHE ((u32)0x00004000) /* Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
5014 #define SDIO_STA_RXFIFOHF ((u32)0x00008000) /* Receive FIFO Half Full: there are at least 8 words in the FIFO */
5015 #define SDIO_STA_TXFIFOF ((u32)0x00010000) /* Transmit FIFO full */
5016 #define SDIO_STA_RXFIFOF ((u32)0x00020000) /* Receive FIFO full */
5017 #define SDIO_STA_TXFIFOE ((u32)0x00040000) /* Transmit FIFO empty */
5018 #define SDIO_STA_RXFIFOE ((u32)0x00080000) /* Receive FIFO empty */
5019 #define SDIO_STA_TXDAVL ((u32)0x00100000) /* Data available in transmit FIFO */
5020 #define SDIO_STA_RXDAVL ((u32)0x00200000) /* Data available in receive FIFO */
5021 #define SDIO_STA_SDIOIT ((u32)0x00400000) /* SDIO interrupt received */
5022 #define SDIO_STA_CEATAEND ((u32)0x00800000) /* CE-ATA command completion signal received for CMD61 */
5023 
5024 
5025 /******************* Bit definition for SDIO_ICR register *******************/
5026 #define SDIO_ICR_CCRCFAILC ((u32)0x00000001) /* CCRCFAIL flag clear bit */
5027 #define SDIO_ICR_DCRCFAILC ((u32)0x00000002) /* DCRCFAIL flag clear bit */
5028 #define SDIO_ICR_CTIMEOUTC ((u32)0x00000004) /* CTIMEOUT flag clear bit */
5029 #define SDIO_ICR_DTIMEOUTC ((u32)0x00000008) /* DTIMEOUT flag clear bit */
5030 #define SDIO_ICR_TXUNDERRC ((u32)0x00000010) /* TXUNDERR flag clear bit */
5031 #define SDIO_ICR_RXOVERRC ((u32)0x00000020) /* RXOVERR flag clear bit */
5032 #define SDIO_ICR_CMDRENDC ((u32)0x00000040) /* CMDREND flag clear bit */
5033 #define SDIO_ICR_CMDSENTC ((u32)0x00000080) /* CMDSENT flag clear bit */
5034 #define SDIO_ICR_DATAENDC ((u32)0x00000100) /* DATAEND flag clear bit */
5035 #define SDIO_ICR_STBITERRC ((u32)0x00000200) /* STBITERR flag clear bit */
5036 #define SDIO_ICR_DBCKENDC ((u32)0x00000400) /* DBCKEND flag clear bit */
5037 #define SDIO_ICR_SDIOITC ((u32)0x00400000) /* SDIOIT flag clear bit */
5038 #define SDIO_ICR_CEATAENDC ((u32)0x00800000) /* CEATAEND flag clear bit */
5039 
5040 
5041 /****************** Bit definition for SDIO_MASK register *******************/
5042 #define SDIO_MASK_CCRCFAILIE ((u32)0x00000001) /* Command CRC Fail Interrupt Enable */
5043 #define SDIO_MASK_DCRCFAILIE ((u32)0x00000002) /* Data CRC Fail Interrupt Enable */
5044 #define SDIO_MASK_CTIMEOUTIE ((u32)0x00000004) /* Command TimeOut Interrupt Enable */
5045 #define SDIO_MASK_DTIMEOUTIE ((u32)0x00000008) /* Data TimeOut Interrupt Enable */
5046 #define SDIO_MASK_TXUNDERRIE ((u32)0x00000010) /* Tx FIFO UnderRun Error Interrupt Enable */
5047 #define SDIO_MASK_RXOVERRIE ((u32)0x00000020) /* Rx FIFO OverRun Error Interrupt Enable */
5048 #define SDIO_MASK_CMDRENDIE ((u32)0x00000040) /* Command Response Received Interrupt Enable */
5049 #define SDIO_MASK_CMDSENTIE ((u32)0x00000080) /* Command Sent Interrupt Enable */
5050 #define SDIO_MASK_DATAENDIE ((u32)0x00000100) /* Data End Interrupt Enable */
5051 #define SDIO_MASK_STBITERRIE ((u32)0x00000200) /* Start Bit Error Interrupt Enable */
5052 #define SDIO_MASK_DBCKENDIE ((u32)0x00000400) /* Data Block End Interrupt Enable */
5053 #define SDIO_MASK_CMDACTIE ((u32)0x00000800) /* CCommand Acting Interrupt Enable */
5054 #define SDIO_MASK_TXACTIE ((u32)0x00001000) /* Data Transmit Acting Interrupt Enable */
5055 #define SDIO_MASK_RXACTIE ((u32)0x00002000) /* Data receive acting interrupt enabled */
5056 #define SDIO_MASK_TXFIFOHEIE ((u32)0x00004000) /* Tx FIFO Half Empty interrupt Enable */
5057 #define SDIO_MASK_RXFIFOHFIE ((u32)0x00008000) /* Rx FIFO Half Full interrupt Enable */
5058 #define SDIO_MASK_TXFIFOFIE ((u32)0x00010000) /* Tx FIFO Full interrupt Enable */
5059 #define SDIO_MASK_RXFIFOFIE ((u32)0x00020000) /* Rx FIFO Full interrupt Enable */
5060 #define SDIO_MASK_TXFIFOEIE ((u32)0x00040000) /* Tx FIFO Empty interrupt Enable */
5061 #define SDIO_MASK_RXFIFOEIE ((u32)0x00080000) /* Rx FIFO Empty interrupt Enable */
5062 #define SDIO_MASK_TXDAVLIE ((u32)0x00100000) /* Data available in Tx FIFO interrupt Enable */
5063 #define SDIO_MASK_RXDAVLIE ((u32)0x00200000) /* Data available in Rx FIFO interrupt Enable */
5064 #define SDIO_MASK_SDIOITIE ((u32)0x00400000) /* SDIO Mode Interrupt Received interrupt Enable */
5065 #define SDIO_MASK_CEATAENDIE ((u32)0x00800000) /* CE-ATA command completion signal received Interrupt Enable */
5066 
5067 
5068 /***************** Bit definition for SDIO_FIFOCNT register *****************/
5069 #define SDIO_FIFOCNT_FIFOCOUNT ((u32)0x00FFFFFF) /* Remaining number of words to be written to or read from the FIFO */
5070 
5071 
5072 /****************** Bit definition for SDIO_FIFO register *******************/
5073 #define SDIO_FIFO_FIFODATA ((u32)0xFFFFFFFF) /* Receive and transmit FIFO data */
5074 
5075 
5076 
5077 /******************************************************************************/
5078 /* */
5079 /* USB */
5080 /* */
5081 /******************************************************************************/
5082 
5083 /* Endpoint-specific registers */
5084 /******************* Bit definition for USB_EP0R register *******************/
5085 #define USB_EP0R_EA ((u16)0x000F) /* Endpoint Address */
5086 
5087 #define USB_EP0R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */
5088 #define USB_EP0R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */
5089 #define USB_EP0R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */
5090 
5091 #define USB_EP0R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */
5092 #define USB_EP0R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */
5093 #define USB_EP0R_EP_KIND ((u16)0x0100) /* Endpoint Kind */
5094 
5095 #define USB_EP0R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */
5096 #define USB_EP0R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */
5097 #define USB_EP0R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */
5098 
5099 #define USB_EP0R_SETUP ((u16)0x0800) /* Setup transaction completed */
5100 
5101 #define USB_EP0R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */
5102 #define USB_EP0R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */
5103 #define USB_EP0R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */
5104 
5105 #define USB_EP0R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */
5106 #define USB_EP0R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */
5107 
5108 
5109 /******************* Bit definition for USB_EP1R register *******************/
5110 #define USB_EP1R_EA ((u16)0x000F) /* Endpoint Address */
5111 
5112 #define USB_EP1R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */
5113 #define USB_EP1R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */
5114 #define USB_EP1R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */
5115 
5116 #define USB_EP1R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */
5117 #define USB_EP1R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */
5118 #define USB_EP1R_EP_KIND ((u16)0x0100) /* Endpoint Kind */
5119 
5120 #define USB_EP1R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */
5121 #define USB_EP1R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */
5122 #define USB_EP1R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */
5123 
5124 #define USB_EP1R_SETUP ((u16)0x0800) /* Setup transaction completed */
5125 
5126 #define USB_EP1R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */
5127 #define USB_EP1R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */
5128 #define USB_EP1R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */
5129 
5130 #define USB_EP1R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */
5131 #define USB_EP1R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */
5132 
5133 
5134 /******************* Bit definition for USB_EP2R register *******************/
5135 #define USB_EP2R_EA ((u16)0x000F) /* Endpoint Address */
5136 
5137 #define USB_EP2R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */
5138 #define USB_EP2R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */
5139 #define USB_EP2R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */
5140 
5141 #define USB_EP2R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */
5142 #define USB_EP2R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */
5143 #define USB_EP2R_EP_KIND ((u16)0x0100) /* Endpoint Kind */
5144 
5145 #define USB_EP2R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */
5146 #define USB_EP2R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */
5147 #define USB_EP2R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */
5148 
5149 #define USB_EP2R_SETUP ((u16)0x0800) /* Setup transaction completed */
5150 
5151 #define USB_EP2R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */
5152 #define USB_EP2R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */
5153 #define USB_EP2R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */
5154 
5155 #define USB_EP2R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */
5156 #define USB_EP2R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */
5157 
5158 
5159 /******************* Bit definition for USB_EP3R register *******************/
5160 #define USB_EP3R_EA ((u16)0x000F) /* Endpoint Address */
5161 
5162 #define USB_EP3R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */
5163 #define USB_EP3R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */
5164 #define USB_EP3R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */
5165 
5166 #define USB_EP3R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */
5167 #define USB_EP3R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */
5168 #define USB_EP3R_EP_KIND ((u16)0x0100) /* Endpoint Kind */
5169 
5170 #define USB_EP3R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */
5171 #define USB_EP3R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */
5172 #define USB_EP3R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */
5173 
5174 #define USB_EP3R_SETUP ((u16)0x0800) /* Setup transaction completed */
5175 
5176 #define USB_EP3R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */
5177 #define USB_EP3R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */
5178 #define USB_EP3R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */
5179 
5180 #define USB_EP3R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */
5181 #define USB_EP3R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */
5182 
5183 
5184 /******************* Bit definition for USB_EP4R register *******************/
5185 #define USB_EP4R_EA ((u16)0x000F) /* Endpoint Address */
5186 
5187 #define USB_EP4R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */
5188 #define USB_EP4R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */
5189 #define USB_EP4R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */
5190 
5191 #define USB_EP4R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */
5192 #define USB_EP4R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */
5193 #define USB_EP4R_EP_KIND ((u16)0x0100) /* Endpoint Kind */
5194 
5195 #define USB_EP4R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */
5196 #define USB_EP4R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */
5197 #define USB_EP4R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */
5198 
5199 #define USB_EP4R_SETUP ((u16)0x0800) /* Setup transaction completed */
5200 
5201 #define USB_EP4R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */
5202 #define USB_EP4R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */
5203 #define USB_EP4R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */
5204 
5205 #define USB_EP4R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */
5206 #define USB_EP4R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */
5207 
5208 
5209 /******************* Bit definition for USB_EP5R register *******************/
5210 #define USB_EP5R_EA ((u16)0x000F) /* Endpoint Address */
5211 
5212 #define USB_EP5R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */
5213 #define USB_EP5R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */
5214 #define USB_EP5R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */
5215 
5216 #define USB_EP5R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */
5217 #define USB_EP5R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */
5218 #define USB_EP5R_EP_KIND ((u16)0x0100) /* Endpoint Kind */
5219 
5220 #define USB_EP5R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */
5221 #define USB_EP5R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */
5222 #define USB_EP5R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */
5223 
5224 #define USB_EP5R_SETUP ((u16)0x0800) /* Setup transaction completed */
5225 
5226 #define USB_EP5R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */
5227 #define USB_EP5R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */
5228 #define USB_EP5R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */
5229 
5230 #define USB_EP5R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */
5231 #define USB_EP5R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */
5232 
5233 
5234 /******************* Bit definition for USB_EP6R register *******************/
5235 #define USB_EP6R_EA ((u16)0x000F) /* Endpoint Address */
5236 
5237 #define USB_EP6R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */
5238 #define USB_EP6R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */
5239 #define USB_EP6R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */
5240 
5241 #define USB_EP6R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */
5242 #define USB_EP6R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */
5243 #define USB_EP6R_EP_KIND ((u16)0x0100) /* Endpoint Kind */
5244 
5245 #define USB_EP6R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */
5246 #define USB_EP6R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */
5247 #define USB_EP6R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */
5248 
5249 #define USB_EP6R_SETUP ((u16)0x0800) /* Setup transaction completed */
5250 
5251 #define USB_EP6R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */
5252 #define USB_EP6R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */
5253 #define USB_EP6R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */
5254 
5255 #define USB_EP6R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */
5256 #define USB_EP6R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */
5257 
5258 
5259 /******************* Bit definition for USB_EP7R register *******************/
5260 #define USB_EP7R_EA ((u16)0x000F) /* Endpoint Address */
5261 
5262 #define USB_EP7R_STAT_TX ((u16)0x0030) /* STAT_TX[1:0] bits (Status bits, for transmission transfers) */
5263 #define USB_EP7R_STAT_TX_0 ((u16)0x0010) /* Bit 0 */
5264 #define USB_EP7R_STAT_TX_1 ((u16)0x0020) /* Bit 1 */
5265 
5266 #define USB_EP7R_DTOG_TX ((u16)0x0040) /* Data Toggle, for transmission transfers */
5267 #define USB_EP7R_CTR_TX ((u16)0x0080) /* Correct Transfer for transmission */
5268 #define USB_EP7R_EP_KIND ((u16)0x0100) /* Endpoint Kind */
5269 
5270 #define USB_EP7R_EP_TYPE ((u16)0x0600) /* EP_TYPE[1:0] bits (Endpoint type) */
5271 #define USB_EP7R_EP_TYPE_0 ((u16)0x0200) /* Bit 0 */
5272 #define USB_EP7R_EP_TYPE_1 ((u16)0x0400) /* Bit 1 */
5273 
5274 #define USB_EP7R_SETUP ((u16)0x0800) /* Setup transaction completed */
5275 
5276 #define USB_EP7R_STAT_RX ((u16)0x3000) /* STAT_RX[1:0] bits (Status bits, for reception transfers) */
5277 #define USB_EP7R_STAT_RX_0 ((u16)0x1000) /* Bit 0 */
5278 #define USB_EP7R_STAT_RX_1 ((u16)0x2000) /* Bit 1 */
5279 
5280 #define USB_EP7R_DTOG_RX ((u16)0x4000) /* Data Toggle, for reception transfers */
5281 #define USB_EP7R_CTR_RX ((u16)0x8000) /* Correct Transfer for reception */
5282 
5283 
5284 /* Common registers */
5285 /******************* Bit definition for USB_CNTR register *******************/
5286 #define USB_CNTR_FRES ((u16)0x0001) /* Force USB Reset */
5287 #define USB_CNTR_PDWN ((u16)0x0002) /* Power down */
5288 #define USB_CNTR_LP_MODE ((u16)0x0004) /* Low-power mode */
5289 #define USB_CNTR_FSUSP ((u16)0x0008) /* Force suspend */
5290 #define USB_CNTR_RESUME ((u16)0x0010) /* Resume request */
5291 #define USB_CNTR_ESOFM ((u16)0x0100) /* Expected Start Of Frame Interrupt Mask */
5292 #define USB_CNTR_SOFM ((u16)0x0200) /* Start Of Frame Interrupt Mask */
5293 #define USB_CNTR_RESETM ((u16)0x0400) /* RESET Interrupt Mask */
5294 #define USB_CNTR_SUSPM ((u16)0x0800) /* Suspend mode Interrupt Mask */
5295 #define USB_CNTR_WKUPM ((u16)0x1000) /* Wakeup Interrupt Mask */
5296 #define USB_CNTR_ERRM ((u16)0x2000) /* Error Interrupt Mask */
5297 #define USB_CNTR_PMAOVRM ((u16)0x4000) /* Packet Memory Area Over / Underrun Interrupt Mask */
5298 #define USB_CNTR_CTRM ((u16)0x8000) /* Correct Transfer Interrupt Mask */
5299 
5300 
5301 /******************* Bit definition for USB_ISTR register *******************/
5302 #define USB_ISTR_EP_ID ((u16)0x000F) /* Endpoint Identifier */
5303 #define USB_ISTR_DIR ((u16)0x0010) /* Direction of transaction */
5304 #define USB_ISTR_ESOF ((u16)0x0100) /* Expected Start Of Frame */
5305 #define USB_ISTR_SOF ((u16)0x0200) /* Start Of Frame */
5306 #define USB_ISTR_RESET ((u16)0x0400) /* USB RESET request */
5307 #define USB_ISTR_SUSP ((u16)0x0800) /* Suspend mode request */
5308 #define USB_ISTR_WKUP ((u16)0x1000) /* Wake up */
5309 #define USB_ISTR_ERR ((u16)0x2000) /* Error */
5310 #define USB_ISTR_PMAOVR ((u16)0x4000) /* Packet Memory Area Over / Underrun */
5311 #define USB_ISTR_CTR ((u16)0x8000) /* Correct Transfer */
5312 
5313 
5314 /******************* Bit definition for USB_FNR register ********************/
5315 #define USB_FNR_FN ((u16)0x07FF) /* Frame Number */
5316 #define USB_FNR_LSOF ((u16)0x1800) /* Lost SOF */
5317 #define USB_FNR_LCK ((u16)0x2000) /* Locked */
5318 #define USB_FNR_RXDM ((u16)0x4000) /* Receive Data - Line Status */
5319 #define USB_FNR_RXDP ((u16)0x8000) /* Receive Data + Line Status */
5320 
5321 
5322 /****************** Bit definition for USB_DADDR register *******************/
5323 #define USB_DADDR_ADD ((u8)0x7F) /* ADD[6:0] bits (Device Address) */
5324 #define USB_DADDR_ADD0 ((u8)0x01) /* Bit 0 */
5325 #define USB_DADDR_ADD1 ((u8)0x02) /* Bit 1 */
5326 #define USB_DADDR_ADD2 ((u8)0x04) /* Bit 2 */
5327 #define USB_DADDR_ADD3 ((u8)0x08) /* Bit 3 */
5328 #define USB_DADDR_ADD4 ((u8)0x10) /* Bit 4 */
5329 #define USB_DADDR_ADD5 ((u8)0x20) /* Bit 5 */
5330 #define USB_DADDR_ADD6 ((u8)0x40) /* Bit 6 */
5331 
5332 #define USB_DADDR_EF ((u8)0x80) /* Enable Function */
5333 
5334 
5335 /****************** Bit definition for USB_BTABLE register ******************/
5336 #define USB_BTABLE_BTABLE ((u16)0xFFF8) /* Buffer Table */
5337 
5338 
5339 /* Buffer descriptor table */
5340 /***************** Bit definition for USB_ADDR0_TX register *****************/
5341 #define USB_ADDR0_TX_ADDR0_TX ((u16)0xFFFE) /* Transmission Buffer Address 0 */
5342 
5343 
5344 /***************** Bit definition for USB_ADDR1_TX register *****************/
5345 #define USB_ADDR1_TX_ADDR1_TX ((u16)0xFFFE) /* Transmission Buffer Address 1 */
5346 
5347 
5348 /***************** Bit definition for USB_ADDR2_TX register *****************/
5349 #define USB_ADDR2_TX_ADDR2_TX ((u16)0xFFFE) /* Transmission Buffer Address 2 */
5350 
5351 
5352 /***************** Bit definition for USB_ADDR3_TX register *****************/
5353 #define USB_ADDR3_TX_ADDR3_TX ((u16)0xFFFE) /* Transmission Buffer Address 3 */
5354 
5355 
5356 /***************** Bit definition for USB_ADDR4_TX register *****************/
5357 #define USB_ADDR4_TX_ADDR4_TX ((u16)0xFFFE) /* Transmission Buffer Address 4 */
5358 
5359 
5360 /***************** Bit definition for USB_ADDR5_TX register *****************/
5361 #define USB_ADDR5_TX_ADDR5_TX ((u16)0xFFFE) /* Transmission Buffer Address 5 */
5362 
5363 
5364 /***************** Bit definition for USB_ADDR6_TX register *****************/
5365 #define USB_ADDR6_TX_ADDR6_TX ((u16)0xFFFE) /* Transmission Buffer Address 6 */
5366 
5367 
5368 /***************** Bit definition for USB_ADDR7_TX register *****************/
5369 #define USB_ADDR7_TX_ADDR7_TX ((u16)0xFFFE) /* Transmission Buffer Address 7 */
5370 
5371 
5372 /*----------------------------------------------------------------------------*/
5373 
5374 
5375 /***************** Bit definition for USB_COUNT0_TX register ****************/
5376 #define USB_COUNT0_TX_COUNT0_TX ((u16)0x03FF) /* Transmission Byte Count 0 */
5377 
5378 
5379 /***************** Bit definition for USB_COUNT1_TX register ****************/
5380 #define USB_COUNT1_TX_COUNT1_TX ((u16)0x03FF) /* Transmission Byte Count 1 */
5381 
5382 
5383 /***************** Bit definition for USB_COUNT2_TX register ****************/
5384 #define USB_COUNT2_TX_COUNT2_TX ((u16)0x03FF) /* Transmission Byte Count 2 */
5385 
5386 
5387 /***************** Bit definition for USB_COUNT3_TX register ****************/
5388 #define USB_COUNT3_TX_COUNT3_TX ((u16)0x03FF) /* Transmission Byte Count 3 */
5389 
5390 
5391 /***************** Bit definition for USB_COUNT4_TX register ****************/
5392 #define USB_COUNT4_TX_COUNT4_TX ((u16)0x03FF) /* Transmission Byte Count 4 */
5393 
5394 /***************** Bit definition for USB_COUNT5_TX register ****************/
5395 #define USB_COUNT5_TX_COUNT5_TX ((u16)0x03FF) /* Transmission Byte Count 5 */
5396 
5397 
5398 /***************** Bit definition for USB_COUNT6_TX register ****************/
5399 #define USB_COUNT6_TX_COUNT6_TX ((u16)0x03FF) /* Transmission Byte Count 6 */
5400 
5401 
5402 /***************** Bit definition for USB_COUNT7_TX register ****************/
5403 #define USB_COUNT7_TX_COUNT7_TX ((u16)0x03FF) /* Transmission Byte Count 7 */
5404 
5405 
5406 /*----------------------------------------------------------------------------*/
5407 
5408 
5409 /**************** Bit definition for USB_COUNT0_TX_0 register ***************/
5410 #define USB_COUNT0_TX_0_COUNT0_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 0 (low) */
5411 
5412 /**************** Bit definition for USB_COUNT0_TX_1 register ***************/
5413 #define USB_COUNT0_TX_1_COUNT0_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 0 (high) */
5414 
5415 
5416 
5417 /**************** Bit definition for USB_COUNT1_TX_0 register ***************/
5418 #define USB_COUNT1_TX_0_COUNT1_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 1 (low) */
5419 
5420 /**************** Bit definition for USB_COUNT1_TX_1 register ***************/
5421 #define USB_COUNT1_TX_1_COUNT1_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 1 (high) */
5422 
5423 
5424 
5425 /**************** Bit definition for USB_COUNT2_TX_0 register ***************/
5426 #define USB_COUNT2_TX_0_COUNT2_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 2 (low) */
5427 
5428 /**************** Bit definition for USB_COUNT2_TX_1 register ***************/
5429 #define USB_COUNT2_TX_1_COUNT2_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 2 (high) */
5430 
5431 
5432 
5433 /**************** Bit definition for USB_COUNT3_TX_0 register ***************/
5434 #define USB_COUNT3_TX_0_COUNT3_TX_0 ((u16)0x000003FF) /* Transmission Byte Count 3 (low) */
5435 
5436 /**************** Bit definition for USB_COUNT3_TX_1 register ***************/
5437 #define USB_COUNT3_TX_1_COUNT3_TX_1 ((u16)0x03FF0000) /* Transmission Byte Count 3 (high) */
5438 
5439 
5440 
5441 /**************** Bit definition for USB_COUNT4_TX_0 register ***************/
5442 #define USB_COUNT4_TX_0_COUNT4_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 4 (low) */
5443 
5444 /**************** Bit definition for USB_COUNT4_TX_1 register ***************/
5445 #define USB_COUNT4_TX_1_COUNT4_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 4 (high) */
5446 
5447 
5448 
5449 /**************** Bit definition for USB_COUNT5_TX_0 register ***************/
5450 #define USB_COUNT5_TX_0_COUNT5_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 5 (low) */
5451 
5452 /**************** Bit definition for USB_COUNT5_TX_1 register ***************/
5453 #define USB_COUNT5_TX_1_COUNT5_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 5 (high) */
5454 
5455 
5456 
5457 /**************** Bit definition for USB_COUNT6_TX_0 register ***************/
5458 #define USB_COUNT6_TX_0_COUNT6_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 6 (low) */
5459 
5460 /**************** Bit definition for USB_COUNT6_TX_1 register ***************/
5461 #define USB_COUNT6_TX_1_COUNT6_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 6 (high) */
5462 
5463 
5464 
5465 /**************** Bit definition for USB_COUNT7_TX_0 register ***************/
5466 #define USB_COUNT7_TX_0_COUNT7_TX_0 ((u32)0x000003FF) /* Transmission Byte Count 7 (low) */
5467 
5468 /**************** Bit definition for USB_COUNT7_TX_1 register ***************/
5469 #define USB_COUNT7_TX_1_COUNT7_TX_1 ((u32)0x03FF0000) /* Transmission Byte Count 7 (high) */
5470 
5471 
5472 /*----------------------------------------------------------------------------*/
5473 
5474 
5475 /***************** Bit definition for USB_ADDR0_RX register *****************/
5476 #define USB_ADDR0_RX_ADDR0_RX ((u16)0xFFFE) /* Reception Buffer Address 0 */
5477 
5478 
5479 /***************** Bit definition for USB_ADDR1_RX register *****************/
5480 #define USB_ADDR1_RX_ADDR1_RX ((u16)0xFFFE) /* Reception Buffer Address 1 */
5481 
5482 
5483 /***************** Bit definition for USB_ADDR2_RX register *****************/
5484 #define USB_ADDR2_RX_ADDR2_RX ((u16)0xFFFE) /* Reception Buffer Address 2 */
5485 
5486 
5487 /***************** Bit definition for USB_ADDR3_RX register *****************/
5488 #define USB_ADDR3_RX_ADDR3_RX ((u16)0xFFFE) /* Reception Buffer Address 3 */
5489 
5490 
5491 /***************** Bit definition for USB_ADDR4_RX register *****************/
5492 #define USB_ADDR4_RX_ADDR4_RX ((u16)0xFFFE) /* Reception Buffer Address 4 */
5493 
5494 
5495 /***************** Bit definition for USB_ADDR5_RX register *****************/
5496 #define USB_ADDR5_RX_ADDR5_RX ((u16)0xFFFE) /* Reception Buffer Address 5 */
5497 
5498 
5499 /***************** Bit definition for USB_ADDR6_RX register *****************/
5500 #define USB_ADDR6_RX_ADDR6_RX ((u16)0xFFFE) /* Reception Buffer Address 6 */
5501 
5502 
5503 /***************** Bit definition for USB_ADDR7_RX register *****************/
5504 #define USB_ADDR7_RX_ADDR7_RX ((u16)0xFFFE) /* Reception Buffer Address 7 */
5505 
5506 
5507 /*----------------------------------------------------------------------------*/
5508 
5509 
5510 /***************** Bit definition for USB_COUNT0_RX register ****************/
5511 #define USB_COUNT0_RX_COUNT0_RX ((u16)0x03FF) /* Reception Byte Count */
5512 
5513 #define USB_COUNT0_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */
5514 #define USB_COUNT0_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */
5515 #define USB_COUNT0_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */
5516 #define USB_COUNT0_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */
5517 #define USB_COUNT0_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */
5518 #define USB_COUNT0_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */
5519 
5520 #define USB_COUNT0_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */
5521 
5522 
5523 /***************** Bit definition for USB_COUNT1_RX register ****************/
5524 #define USB_COUNT1_RX_COUNT1_RX ((u16)0x03FF) /* Reception Byte Count */
5525 
5526 #define USB_COUNT1_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */
5527 #define USB_COUNT1_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */
5528 #define USB_COUNT1_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */
5529 #define USB_COUNT1_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */
5530 #define USB_COUNT1_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */
5531 #define USB_COUNT1_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */
5532 
5533 #define USB_COUNT1_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */
5534 
5535 
5536 /***************** Bit definition for USB_COUNT2_RX register ****************/
5537 #define USB_COUNT2_RX_COUNT2_RX ((u16)0x03FF) /* Reception Byte Count */
5538 
5539 #define USB_COUNT2_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */
5540 #define USB_COUNT2_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */
5541 #define USB_COUNT2_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */
5542 #define USB_COUNT2_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */
5543 #define USB_COUNT2_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */
5544 #define USB_COUNT2_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */
5545 
5546 #define USB_COUNT2_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */
5547 
5548 
5549 /***************** Bit definition for USB_COUNT3_RX register ****************/
5550 #define USB_COUNT3_RX_COUNT3_RX ((u16)0x03FF) /* Reception Byte Count */
5551 
5552 #define USB_COUNT3_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */
5553 #define USB_COUNT3_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */
5554 #define USB_COUNT3_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */
5555 #define USB_COUNT3_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */
5556 #define USB_COUNT3_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */
5557 #define USB_COUNT3_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */
5558 
5559 #define USB_COUNT3_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */
5560 
5561 
5562 /***************** Bit definition for USB_COUNT4_RX register ****************/
5563 #define USB_COUNT4_RX_COUNT4_RX ((u16)0x03FF) /* Reception Byte Count */
5564 
5565 #define USB_COUNT4_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */
5566 #define USB_COUNT4_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */
5567 #define USB_COUNT4_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */
5568 #define USB_COUNT4_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */
5569 #define USB_COUNT4_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */
5570 #define USB_COUNT4_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */
5571 
5572 #define USB_COUNT4_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */
5573 
5574 
5575 /***************** Bit definition for USB_COUNT5_RX register ****************/
5576 #define USB_COUNT5_RX_COUNT5_RX ((u16)0x03FF) /* Reception Byte Count */
5577 
5578 #define USB_COUNT5_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */
5579 #define USB_COUNT5_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */
5580 #define USB_COUNT5_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */
5581 #define USB_COUNT5_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */
5582 #define USB_COUNT5_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */
5583 #define USB_COUNT5_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */
5584 
5585 #define USB_COUNT5_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */
5586 
5587 /***************** Bit definition for USB_COUNT6_RX register ****************/
5588 #define USB_COUNT6_RX_COUNT6_RX ((u16)0x03FF) /* Reception Byte Count */
5589 
5590 #define USB_COUNT6_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */
5591 #define USB_COUNT6_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */
5592 #define USB_COUNT6_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */
5593 #define USB_COUNT6_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */
5594 #define USB_COUNT6_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */
5595 #define USB_COUNT6_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */
5596 
5597 #define USB_COUNT6_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */
5598 
5599 
5600 /***************** Bit definition for USB_COUNT7_RX register ****************/
5601 #define USB_COUNT7_RX_COUNT7_RX ((u16)0x03FF) /* Reception Byte Count */
5602 
5603 #define USB_COUNT7_RX_NUM_BLOCK ((u16)0x7C00) /* NUM_BLOCK[4:0] bits (Number of blocks) */
5604 #define USB_COUNT7_RX_NUM_BLOCK_0 ((u16)0x0400) /* Bit 0 */
5605 #define USB_COUNT7_RX_NUM_BLOCK_1 ((u16)0x0800) /* Bit 1 */
5606 #define USB_COUNT7_RX_NUM_BLOCK_2 ((u16)0x1000) /* Bit 2 */
5607 #define USB_COUNT7_RX_NUM_BLOCK_3 ((u16)0x2000) /* Bit 3 */
5608 #define USB_COUNT7_RX_NUM_BLOCK_4 ((u16)0x4000) /* Bit 4 */
5609 
5610 #define USB_COUNT7_RX_BLSIZE ((u16)0x8000) /* BLock SIZE */
5611 
5612 
5613 /*----------------------------------------------------------------------------*/
5614 
5615 
5616 /**************** Bit definition for USB_COUNT0_RX_0 register ***************/
5617 #define USB_COUNT0_RX_0_COUNT0_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */
5618 
5619 #define USB_COUNT0_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5620 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */
5621 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */
5622 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */
5623 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */
5624 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */
5625 
5626 #define USB_COUNT0_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */
5627 
5628 /**************** Bit definition for USB_COUNT0_RX_1 register ***************/
5629 #define USB_COUNT0_RX_1_COUNT0_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */
5630 
5631 #define USB_COUNT0_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5632 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 1 */
5633 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */
5634 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */
5635 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */
5636 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */
5637 
5638 #define USB_COUNT0_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */
5639 
5640 
5641 
5642 /**************** Bit definition for USB_COUNT1_RX_0 register ***************/
5643 #define USB_COUNT1_RX_0_COUNT1_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */
5644 
5645 #define USB_COUNT1_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5646 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */
5647 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */
5648 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */
5649 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */
5650 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */
5651 
5652 #define USB_COUNT1_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */
5653 
5654 /**************** Bit definition for USB_COUNT1_RX_1 register ***************/
5655 #define USB_COUNT1_RX_1_COUNT1_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */
5656 
5657 #define USB_COUNT1_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5658 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */
5659 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */
5660 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */
5661 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */
5662 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */
5663 
5664 #define USB_COUNT1_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */
5665 
5666 
5667 
5668 /**************** Bit definition for USB_COUNT2_RX_0 register ***************/
5669 #define USB_COUNT2_RX_0_COUNT2_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */
5670 
5671 #define USB_COUNT2_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5672 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */
5673 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */
5674 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */
5675 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */
5676 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */
5677 
5678 #define USB_COUNT2_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */
5679 
5680 /**************** Bit definition for USB_COUNT2_RX_1 register ***************/
5681 #define USB_COUNT2_RX_1_COUNT2_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */
5682 
5683 #define USB_COUNT2_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5684 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */
5685 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */
5686 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */
5687 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */
5688 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */
5689 
5690 #define USB_COUNT2_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */
5691 
5692 
5693 
5694 /**************** Bit definition for USB_COUNT3_RX_0 register ***************/
5695 #define USB_COUNT3_RX_0_COUNT3_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */
5696 
5697 #define USB_COUNT3_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5698 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */
5699 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */
5700 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */
5701 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */
5702 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */
5703 
5704 #define USB_COUNT3_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */
5705 
5706 /**************** Bit definition for USB_COUNT3_RX_1 register ***************/
5707 #define USB_COUNT3_RX_1_COUNT3_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */
5708 
5709 #define USB_COUNT3_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5710 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */
5711 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */
5712 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */
5713 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */
5714 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */
5715 
5716 #define USB_COUNT3_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */
5717 
5718 
5719 
5720 /**************** Bit definition for USB_COUNT4_RX_0 register ***************/
5721 #define USB_COUNT4_RX_0_COUNT4_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */
5722 
5723 #define USB_COUNT4_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5724 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */
5725 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */
5726 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */
5727 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */
5728 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */
5729 
5730 #define USB_COUNT4_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */
5731 
5732 /**************** Bit definition for USB_COUNT4_RX_1 register ***************/
5733 #define USB_COUNT4_RX_1_COUNT4_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */
5734 
5735 #define USB_COUNT4_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5736 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */
5737 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */
5738 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */
5739 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */
5740 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */
5741 
5742 #define USB_COUNT4_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */
5743 
5744 
5745 
5746 /**************** Bit definition for USB_COUNT5_RX_0 register ***************/
5747 #define USB_COUNT5_RX_0_COUNT5_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */
5748 
5749 #define USB_COUNT5_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5750 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */
5751 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */
5752 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */
5753 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */
5754 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */
5755 
5756 #define USB_COUNT5_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */
5757 
5758 /**************** Bit definition for USB_COUNT5_RX_1 register ***************/
5759 #define USB_COUNT5_RX_1_COUNT5_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */
5760 
5761 #define USB_COUNT5_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5762 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */
5763 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */
5764 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */
5765 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */
5766 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */
5767 
5768 #define USB_COUNT5_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */
5769 
5770 
5771 
5772 /*************** Bit definition for USB_COUNT6_RX_0 register ***************/
5773 #define USB_COUNT6_RX_0_COUNT6_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */
5774 
5775 #define USB_COUNT6_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5776 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */
5777 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */
5778 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */
5779 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */
5780 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */
5781 
5782 #define USB_COUNT6_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */
5783 
5784 /**************** Bit definition for USB_COUNT6_RX_1 register ***************/
5785 #define USB_COUNT6_RX_1_COUNT6_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */
5786 
5787 #define USB_COUNT6_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5788 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */
5789 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */
5790 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */
5791 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */
5792 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */
5793 
5794 #define USB_COUNT6_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */
5795 
5796 
5797 
5798 /*************** Bit definition for USB_COUNT7_RX_0 register ****************/
5799 #define USB_COUNT7_RX_0_COUNT7_RX_0 ((u32)0x000003FF) /* Reception Byte Count (low) */
5800 
5801 #define USB_COUNT7_RX_0_NUM_BLOCK_0 ((u32)0x00007C00) /* NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5802 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((u32)0x00000400) /* Bit 0 */
5803 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((u32)0x00000800) /* Bit 1 */
5804 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((u32)0x00001000) /* Bit 2 */
5805 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((u32)0x00002000) /* Bit 3 */
5806 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((u32)0x00004000) /* Bit 4 */
5807 
5808 #define USB_COUNT7_RX_0_BLSIZE_0 ((u32)0x00008000) /* BLock SIZE (low) */
5809 
5810 /*************** Bit definition for USB_COUNT7_RX_1 register ****************/
5811 #define USB_COUNT7_RX_1_COUNT7_RX_1 ((u32)0x03FF0000) /* Reception Byte Count (high) */
5812 
5813 #define USB_COUNT7_RX_1_NUM_BLOCK_1 ((u32)0x7C000000) /* NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5814 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((u32)0x04000000) /* Bit 0 */
5815 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((u32)0x08000000) /* Bit 1 */
5816 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((u32)0x10000000) /* Bit 2 */
5817 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((u32)0x20000000) /* Bit 3 */
5818 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((u32)0x40000000) /* Bit 4 */
5819 
5820 #define USB_COUNT7_RX_1_BLSIZE_1 ((u32)0x80000000) /* BLock SIZE (high) */
5821 
5822 
5823 
5824 /******************************************************************************/
5825 /* */
5826 /* Controller Area Network */
5827 /* */
5828 /******************************************************************************/
5829 
5830 /* CAN control and status registers */
5831 /******************* Bit definition for CAN_MCR register ********************/
5832 #define CAN_MCR_INRQ ((u16)0x0001) /* Initialization Request */
5833 #define CAN_MCR_SLEEP ((u16)0x0002) /* Sleep Mode Request */
5834 #define CAN_MCR_TXFP ((u16)0x0004) /* Transmit FIFO Priority */
5835 #define CAN_MCR_RFLM ((u16)0x0008) /* Receive FIFO Locked Mode */
5836 #define CAN_MCR_NART ((u16)0x0010) /* No Automatic Retransmission */
5837 #define CAN_MCR_AWUM ((u16)0x0020) /* Automatic Wakeup Mode */
5838 #define CAN_MCR_ABOM ((u16)0x0040) /* Automatic Bus-Off Management */
5839 #define CAN_MCR_TTCM ((u16)0x0080) /* Time Triggered Communication Mode */
5840 #define CAN_MCR_RESET ((u16)0x8000) /* bxCAN software master reset */
5841 
5842 
5843 /******************* Bit definition for CAN_MSR register ********************/
5844 #define CAN_MSR_INAK ((u16)0x0001) /* Initialization Acknowledge */
5845 #define CAN_MSR_SLAK ((u16)0x0002) /* Sleep Acknowledge */
5846 #define CAN_MSR_ERRI ((u16)0x0004) /* Error Interrupt */
5847 #define CAN_MSR_WKUI ((u16)0x0008) /* Wakeup Interrupt */
5848 #define CAN_MSR_SLAKI ((u16)0x0010) /* Sleep Acknowledge Interrupt */
5849 #define CAN_MSR_TXM ((u16)0x0100) /* Transmit Mode */
5850 #define CAN_MSR_RXM ((u16)0x0200) /* Receive Mode */
5851 #define CAN_MSR_SAMP ((u16)0x0400) /* Last Sample Point */
5852 #define CAN_MSR_RX ((u16)0x0800) /* CAN Rx Signal */
5853 
5854 
5855 /******************* Bit definition for CAN_TSR register ********************/
5856 #define CAN_TSR_RQCP0 ((u32)0x00000001) /* Request Completed Mailbox0 */
5857 #define CAN_TSR_TXOK0 ((u32)0x00000002) /* Transmission OK of Mailbox0 */
5858 #define CAN_TSR_ALST0 ((u32)0x00000004) /* Arbitration Lost for Mailbox0 */
5859 #define CAN_TSR_TERR0 ((u32)0x00000008) /* Transmission Error of Mailbox0 */
5860 #define CAN_TSR_ABRQ0 ((u32)0x00000080) /* Abort Request for Mailbox0 */
5861 #define CAN_TSR_RQCP1 ((u32)0x00000100) /* Request Completed Mailbox1 */
5862 #define CAN_TSR_TXOK1 ((u32)0x00000200) /* Transmission OK of Mailbox1 */
5863 #define CAN_TSR_ALST1 ((u32)0x00000400) /* Arbitration Lost for Mailbox1 */
5864 #define CAN_TSR_TERR1 ((u32)0x00000800) /* Transmission Error of Mailbox1 */
5865 #define CAN_TSR_ABRQ1 ((u32)0x00008000) /* Abort Request for Mailbox 1 */
5866 #define CAN_TSR_RQCP2 ((u32)0x00010000) /* Request Completed Mailbox2 */
5867 #define CAN_TSR_TXOK2 ((u32)0x00020000) /* Transmission OK of Mailbox 2 */
5868 #define CAN_TSR_ALST2 ((u32)0x00040000) /* Arbitration Lost for mailbox 2 */
5869 #define CAN_TSR_TERR2 ((u32)0x00080000) /* Transmission Error of Mailbox 2 */
5870 #define CAN_TSR_ABRQ2 ((u32)0x00800000) /* Abort Request for Mailbox 2 */
5871 #define CAN_TSR_CODE ((u32)0x03000000) /* Mailbox Code */
5872 
5873 #define CAN_TSR_TME ((u32)0x1C000000) /* TME[2:0] bits */
5874 #define CAN_TSR_TME0 ((u32)0x04000000) /* Transmit Mailbox 0 Empty */
5875 #define CAN_TSR_TME1 ((u32)0x08000000) /* Transmit Mailbox 1 Empty */
5876 #define CAN_TSR_TME2 ((u32)0x10000000) /* Transmit Mailbox 2 Empty */
5877 
5878 #define CAN_TSR_LOW ((u32)0xE0000000) /* LOW[2:0] bits */
5879 #define CAN_TSR_LOW0 ((u32)0x20000000) /* Lowest Priority Flag for Mailbox 0 */
5880 #define CAN_TSR_LOW1 ((u32)0x40000000) /* Lowest Priority Flag for Mailbox 1 */
5881 #define CAN_TSR_LOW2 ((u32)0x80000000) /* Lowest Priority Flag for Mailbox 2 */
5882 
5883 
5884 /******************* Bit definition for CAN_RF0R register *******************/
5885 #define CAN_RF0R_FMP0 ((u8)0x03) /* FIFO 0 Message Pending */
5886 #define CAN_RF0R_FULL0 ((u8)0x08) /* FIFO 0 Full */
5887 #define CAN_RF0R_FOVR0 ((u8)0x10) /* FIFO 0 Overrun */
5888 #define CAN_RF0R_RFOM0 ((u8)0x20) /* Release FIFO 0 Output Mailbox */
5889 
5890 
5891 /******************* Bit definition for CAN_RF1R register *******************/
5892 #define CAN_RF1R_FMP1 ((u8)0x03) /* FIFO 1 Message Pending */
5893 #define CAN_RF1R_FULL1 ((u8)0x08) /* FIFO 1 Full */
5894 #define CAN_RF1R_FOVR1 ((u8)0x10) /* FIFO 1 Overrun */
5895 #define CAN_RF1R_RFOM1 ((u8)0x20) /* Release FIFO 1 Output Mailbox */
5896 
5897 
5898 /******************** Bit definition for CAN_IER register *******************/
5899 #define CAN_IER_TMEIE ((u32)0x00000001) /* Transmit Mailbox Empty Interrupt Enable */
5900 #define CAN_IER_FMPIE0 ((u32)0x00000002) /* FIFO Message Pending Interrupt Enable */
5901 #define CAN_IER_FFIE0 ((u32)0x00000004) /* FIFO Full Interrupt Enable */
5902 #define CAN_IER_FOVIE0 ((u32)0x00000008) /* FIFO Overrun Interrupt Enable */
5903 #define CAN_IER_FMPIE1 ((u32)0x00000010) /* FIFO Message Pending Interrupt Enable */
5904 #define CAN_IER_FFIE1 ((u32)0x00000020) /* FIFO Full Interrupt Enable */
5905 #define CAN_IER_FOVIE1 ((u32)0x00000040) /* FIFO Overrun Interrupt Enable */
5906 #define CAN_IER_EWGIE ((u32)0x00000100) /* Error Warning Interrupt Enable */
5907 #define CAN_IER_EPVIE ((u32)0x00000200) /* Error Passive Interrupt Enable */
5908 #define CAN_IER_BOFIE ((u32)0x00000400) /* Bus-Off Interrupt Enable */
5909 #define CAN_IER_LECIE ((u32)0x00000800) /* Last Error Code Interrupt Enable */
5910 #define CAN_IER_ERRIE ((u32)0x00008000) /* Error Interrupt Enable */
5911 #define CAN_IER_WKUIE ((u32)0x00010000) /* Wakeup Interrupt Enable */
5912 #define CAN_IER_SLKIE ((u32)0x00020000) /* Sleep Interrupt Enable */
5913 
5914 
5915 /******************** Bit definition for CAN_ESR register *******************/
5916 #define CAN_ESR_EWGF ((u32)0x00000001) /* Error Warning Flag */
5917 #define CAN_ESR_EPVF ((u32)0x00000002) /* Error Passive Flag */
5918 #define CAN_ESR_BOFF ((u32)0x00000004) /* Bus-Off Flag */
5919 
5920 #define CAN_ESR_LEC ((u32)0x00000070) /* LEC[2:0] bits (Last Error Code) */
5921 #define CAN_ESR_LEC_0 ((u32)0x00000010) /* Bit 0 */
5922 #define CAN_ESR_LEC_1 ((u32)0x00000020) /* Bit 1 */
5923 #define CAN_ESR_LEC_2 ((u32)0x00000040) /* Bit 2 */
5924 
5925 #define CAN_ESR_TEC ((u32)0x00FF0000) /* Least significant byte of the 9-bit Transmit Error Counter */
5926 #define CAN_ESR_REC ((u32)0xFF000000) /* Receive Error Counter */
5927 
5928 
5929 /******************* Bit definition for CAN_BTR register ********************/
5930 #define CAN_BTR_BRP ((u32)0x000003FF) /* Baud Rate Prescaler */
5931 #define CAN_BTR_TS1 ((u32)0x000F0000) /* Time Segment 1 */
5932 #define CAN_BTR_TS2 ((u32)0x00700000) /* Time Segment 2 */
5933 #define CAN_BTR_SJW ((u32)0x03000000) /* Resynchronization Jump Width */
5934 #define CAN_BTR_LBKM ((u32)0x40000000) /* Loop Back Mode (Debug) */
5935 #define CAN_BTR_SILM ((u32)0x80000000) /* Silent Mode */
5936 
5937 
5938 /* Mailbox registers */
5939 /****************** Bit definition for CAN_TI0R register ********************/
5940 #define CAN_TI0R_TXRQ ((u32)0x00000001) /* Transmit Mailbox Request */
5941 #define CAN_TI0R_RTR ((u32)0x00000002) /* Remote Transmission Request */
5942 #define CAN_TI0R_IDE ((u32)0x00000004) /* Identifier Extension */
5943 #define CAN_TI0R_EXID ((u32)0x001FFFF8) /* Extended Identifier */
5944 #define CAN_TI0R_STID ((u32)0xFFE00000) /* Standard Identifier or Extended Identifier */
5945 
5946 
5947 /****************** Bit definition for CAN_TDT0R register *******************/
5948 #define CAN_TDT0R_DLC ((u32)0x0000000F) /* Data Length Code */
5949 #define CAN_TDT0R_TGT ((u32)0x00000100) /* Transmit Global Time */
5950 #define CAN_TDT0R_TIME ((u32)0xFFFF0000) /* Message Time Stamp */
5951 
5952 
5953 /****************** Bit definition for CAN_TDL0R register *******************/
5954 #define CAN_TDL0R_DATA0 ((u32)0x000000FF) /* Data byte 0 */
5955 #define CAN_TDL0R_DATA1 ((u32)0x0000FF00) /* Data byte 1 */
5956 #define CAN_TDL0R_DATA2 ((u32)0x00FF0000) /* Data byte 2 */
5957 #define CAN_TDL0R_DATA3 ((u32)0xFF000000) /* Data byte 3 */
5958 
5959 
5960 /****************** Bit definition for CAN_TDH0R register *******************/
5961 #define CAN_TDH0R_DATA4 ((u32)0x000000FF) /* Data byte 4 */
5962 #define CAN_TDH0R_DATA5 ((u32)0x0000FF00) /* Data byte 5 */
5963 #define CAN_TDH0R_DATA6 ((u32)0x00FF0000) /* Data byte 6 */
5964 #define CAN_TDH0R_DATA7 ((u32)0xFF000000) /* Data byte 7 */
5965 
5966 
5967 /******************* Bit definition for CAN_TI1R register *******************/
5968 #define CAN_TI1R_TXRQ ((u32)0x00000001) /* Transmit Mailbox Request */
5969 #define CAN_TI1R_RTR ((u32)0x00000002) /* Remote Transmission Request */
5970 #define CAN_TI1R_IDE ((u32)0x00000004) /* Identifier Extension */
5971 #define CAN_TI1R_EXID ((u32)0x001FFFF8) /* Extended Identifier */
5972 #define CAN_TI1R_STID ((u32)0xFFE00000) /* Standard Identifier or Extended Identifier */
5973 
5974 
5975 /******************* Bit definition for CAN_TDT1R register ******************/
5976 #define CAN_TDT1R_DLC ((u32)0x0000000F) /* Data Length Code */
5977 #define CAN_TDT1R_TGT ((u32)0x00000100) /* Transmit Global Time */
5978 #define CAN_TDT1R_TIME ((u32)0xFFFF0000) /* Message Time Stamp */
5979 
5980 
5981 /******************* Bit definition for CAN_TDL1R register ******************/
5982 #define CAN_TDL1R_DATA0 ((u32)0x000000FF) /* Data byte 0 */
5983 #define CAN_TDL1R_DATA1 ((u32)0x0000FF00) /* Data byte 1 */
5984 #define CAN_TDL1R_DATA2 ((u32)0x00FF0000) /* Data byte 2 */
5985 #define CAN_TDL1R_DATA3 ((u32)0xFF000000) /* Data byte 3 */
5986 
5987 
5988 /******************* Bit definition for CAN_TDH1R register ******************/
5989 #define CAN_TDH1R_DATA4 ((u32)0x000000FF) /* Data byte 4 */
5990 #define CAN_TDH1R_DATA5 ((u32)0x0000FF00) /* Data byte 5 */
5991 #define CAN_TDH1R_DATA6 ((u32)0x00FF0000) /* Data byte 6 */
5992 #define CAN_TDH1R_DATA7 ((u32)0xFF000000) /* Data byte 7 */
5993 
5994 
5995 /******************* Bit definition for CAN_TI2R register *******************/
5996 #define CAN_TI2R_TXRQ ((u32)0x00000001) /* Transmit Mailbox Request */
5997 #define CAN_TI2R_RTR ((u32)0x00000002) /* Remote Transmission Request */
5998 #define CAN_TI2R_IDE ((u32)0x00000004) /* Identifier Extension */
5999 #define CAN_TI2R_EXID ((u32)0x001FFFF8) /* Extended identifier */
6000 #define CAN_TI2R_STID ((u32)0xFFE00000) /* Standard Identifier or Extended Identifier */
6001 
6002 
6003 /******************* Bit definition for CAN_TDT2R register ******************/
6004 #define CAN_TDT2R_DLC ((u32)0x0000000F) /* Data Length Code */
6005 #define CAN_TDT2R_TGT ((u32)0x00000100) /* Transmit Global Time */
6006 #define CAN_TDT2R_TIME ((u32)0xFFFF0000) /* Message Time Stamp */
6007 
6008 
6009 /******************* Bit definition for CAN_TDL2R register ******************/
6010 #define CAN_TDL2R_DATA0 ((u32)0x000000FF) /* Data byte 0 */
6011 #define CAN_TDL2R_DATA1 ((u32)0x0000FF00) /* Data byte 1 */
6012 #define CAN_TDL2R_DATA2 ((u32)0x00FF0000) /* Data byte 2 */
6013 #define CAN_TDL2R_DATA3 ((u32)0xFF000000) /* Data byte 3 */
6014 
6015 
6016 /******************* Bit definition for CAN_TDH2R register ******************/
6017 #define CAN_TDH2R_DATA4 ((u32)0x000000FF) /* Data byte 4 */
6018 #define CAN_TDH2R_DATA5 ((u32)0x0000FF00) /* Data byte 5 */
6019 #define CAN_TDH2R_DATA6 ((u32)0x00FF0000) /* Data byte 6 */
6020 #define CAN_TDH2R_DATA7 ((u32)0xFF000000) /* Data byte 7 */
6021 
6022 
6023 /******************* Bit definition for CAN_RI0R register *******************/
6024 #define CAN_RI0R_RTR ((u32)0x00000002) /* Remote Transmission Request */
6025 #define CAN_RI0R_IDE ((u32)0x00000004) /* Identifier Extension */
6026 #define CAN_RI0R_EXID ((u32)0x001FFFF8) /* Extended Identifier */
6027 #define CAN_RI0R_STID ((u32)0xFFE00000) /* Standard Identifier or Extended Identifier */
6028 
6029 
6030 /******************* Bit definition for CAN_RDT0R register ******************/
6031 #define CAN_RDT0R_DLC ((u32)0x0000000F) /* Data Length Code */
6032 #define CAN_RDT0R_FMI ((u32)0x0000FF00) /* Filter Match Index */
6033 #define CAN_RDT0R_TIME ((u32)0xFFFF0000) /* Message Time Stamp */
6034 
6035 
6036 /******************* Bit definition for CAN_RDL0R register ******************/
6037 #define CAN_RDL0R_DATA0 ((u32)0x000000FF) /* Data byte 0 */
6038 #define CAN_RDL0R_DATA1 ((u32)0x0000FF00) /* Data byte 1 */
6039 #define CAN_RDL0R_DATA2 ((u32)0x00FF0000) /* Data byte 2 */
6040 #define CAN_RDL0R_DATA3 ((u32)0xFF000000) /* Data byte 3 */
6041 
6042 
6043 /******************* Bit definition for CAN_RDH0R register ******************/
6044 #define CAN_RDH0R_DATA4 ((u32)0x000000FF) /* Data byte 4 */
6045 #define CAN_RDH0R_DATA5 ((u32)0x0000FF00) /* Data byte 5 */
6046 #define CAN_RDH0R_DATA6 ((u32)0x00FF0000) /* Data byte 6 */
6047 #define CAN_RDH0R_DATA7 ((u32)0xFF000000) /* Data byte 7 */
6048 
6049 
6050 /******************* Bit definition for CAN_RI1R register *******************/
6051 #define CAN_RI1R_RTR ((u32)0x00000002) /* Remote Transmission Request */
6052 #define CAN_RI1R_IDE ((u32)0x00000004) /* Identifier Extension */
6053 #define CAN_RI1R_EXID ((u32)0x001FFFF8) /* Extended identifier */
6054 #define CAN_RI1R_STID ((u32)0xFFE00000) /* Standard Identifier or Extended Identifier */
6055 
6056 
6057 /******************* Bit definition for CAN_RDT1R register ******************/
6058 #define CAN_RDT1R_DLC ((u32)0x0000000F) /* Data Length Code */
6059 #define CAN_RDT1R_FMI ((u32)0x0000FF00) /* Filter Match Index */
6060 #define CAN_RDT1R_TIME ((u32)0xFFFF0000) /* Message Time Stamp */
6061 
6062 
6063 /******************* Bit definition for CAN_RDL1R register ******************/
6064 #define CAN_RDL1R_DATA0 ((u32)0x000000FF) /* Data byte 0 */
6065 #define CAN_RDL1R_DATA1 ((u32)0x0000FF00) /* Data byte 1 */
6066 #define CAN_RDL1R_DATA2 ((u32)0x00FF0000) /* Data byte 2 */
6067 #define CAN_RDL1R_DATA3 ((u32)0xFF000000) /* Data byte 3 */
6068 
6069 
6070 /******************* Bit definition for CAN_RDH1R register ******************/
6071 #define CAN_RDH1R_DATA4 ((u32)0x000000FF) /* Data byte 4 */
6072 #define CAN_RDH1R_DATA5 ((u32)0x0000FF00) /* Data byte 5 */
6073 #define CAN_RDH1R_DATA6 ((u32)0x00FF0000) /* Data byte 6 */
6074 #define CAN_RDH1R_DATA7 ((u32)0xFF000000) /* Data byte 7 */
6075 
6076 /* CAN filter registers */
6077 /******************* Bit definition for CAN_FMR register ********************/
6078 #define CAN_FMR_FINIT ((u8)0x01) /* Filter Init Mode */
6079 
6080 
6081 /******************* Bit definition for CAN_FM1R register *******************/
6082 #define CAN_FM1R_FBM ((u16)0x3FFF) /* Filter Mode */
6083 #define CAN_FM1R_FBM0 ((u16)0x0001) /* Filter Init Mode bit 0 */
6084 #define CAN_FM1R_FBM1 ((u16)0x0002) /* Filter Init Mode bit 1 */
6085 #define CAN_FM1R_FBM2 ((u16)0x0004) /* Filter Init Mode bit 2 */
6086 #define CAN_FM1R_FBM3 ((u16)0x0008) /* Filter Init Mode bit 3 */
6087 #define CAN_FM1R_FBM4 ((u16)0x0010) /* Filter Init Mode bit 4 */
6088 #define CAN_FM1R_FBM5 ((u16)0x0020) /* Filter Init Mode bit 5 */
6089 #define CAN_FM1R_FBM6 ((u16)0x0040) /* Filter Init Mode bit 6 */
6090 #define CAN_FM1R_FBM7 ((u16)0x0080) /* Filter Init Mode bit 7 */
6091 #define CAN_FM1R_FBM8 ((u16)0x0100) /* Filter Init Mode bit 8 */
6092 #define CAN_FM1R_FBM9 ((u16)0x0200) /* Filter Init Mode bit 9 */
6093 #define CAN_FM1R_FBM10 ((u16)0x0400) /* Filter Init Mode bit 10 */
6094 #define CAN_FM1R_FBM11 ((u16)0x0800) /* Filter Init Mode bit 11 */
6095 #define CAN_FM1R_FBM12 ((u16)0x1000) /* Filter Init Mode bit 12 */
6096 #define CAN_FM1R_FBM13 ((u16)0x2000) /* Filter Init Mode bit 13 */
6097 
6098 
6099 /******************* Bit definition for CAN_FS1R register *******************/
6100 #define CAN_FS1R_FSC ((u16)0x3FFF) /* Filter Scale Configuration */
6101 #define CAN_FS1R_FSC0 ((u16)0x0001) /* Filter Scale Configuration bit 0 */
6102 #define CAN_FS1R_FSC1 ((u16)0x0002) /* Filter Scale Configuration bit 1 */
6103 #define CAN_FS1R_FSC2 ((u16)0x0004) /* Filter Scale Configuration bit 2 */
6104 #define CAN_FS1R_FSC3 ((u16)0x0008) /* Filter Scale Configuration bit 3 */
6105 #define CAN_FS1R_FSC4 ((u16)0x0010) /* Filter Scale Configuration bit 4 */
6106 #define CAN_FS1R_FSC5 ((u16)0x0020) /* Filter Scale Configuration bit 5 */
6107 #define CAN_FS1R_FSC6 ((u16)0x0040) /* Filter Scale Configuration bit 6 */
6108 #define CAN_FS1R_FSC7 ((u16)0x0080) /* Filter Scale Configuration bit 7 */
6109 #define CAN_FS1R_FSC8 ((u16)0x0100) /* Filter Scale Configuration bit 8 */
6110 #define CAN_FS1R_FSC9 ((u16)0x0200) /* Filter Scale Configuration bit 9 */
6111 #define CAN_FS1R_FSC10 ((u16)0x0400) /* Filter Scale Configuration bit 10 */
6112 #define CAN_FS1R_FSC11 ((u16)0x0800) /* Filter Scale Configuration bit 11 */
6113 #define CAN_FS1R_FSC12 ((u16)0x1000) /* Filter Scale Configuration bit 12 */
6114 #define CAN_FS1R_FSC13 ((u16)0x2000) /* Filter Scale Configuration bit 13 */
6115 
6116 
6117 /****************** Bit definition for CAN_FFA1R register *******************/
6118 #define CAN_FFA1R_FFA ((u16)0x3FFF) /* Filter FIFO Assignment */
6119 #define CAN_FFA1R_FFA0 ((u16)0x0001) /* Filter FIFO Assignment for Filter 0 */
6120 #define CAN_FFA1R_FFA1 ((u16)0x0002) /* Filter FIFO Assignment for Filter 1 */
6121 #define CAN_FFA1R_FFA2 ((u16)0x0004) /* Filter FIFO Assignment for Filter 2 */
6122 #define CAN_FFA1R_FFA3 ((u16)0x0008) /* Filter FIFO Assignment for Filter 3 */
6123 #define CAN_FFA1R_FFA4 ((u16)0x0010) /* Filter FIFO Assignment for Filter 4 */
6124 #define CAN_FFA1R_FFA5 ((u16)0x0020) /* Filter FIFO Assignment for Filter 5 */
6125 #define CAN_FFA1R_FFA6 ((u16)0x0040) /* Filter FIFO Assignment for Filter 6 */
6126 #define CAN_FFA1R_FFA7 ((u16)0x0080) /* Filter FIFO Assignment for Filter 7 */
6127 #define CAN_FFA1R_FFA8 ((u16)0x0100) /* Filter FIFO Assignment for Filter 8 */
6128 #define CAN_FFA1R_FFA9 ((u16)0x0200) /* Filter FIFO Assignment for Filter 9 */
6129 #define CAN_FFA1R_FFA10 ((u16)0x0400) /* Filter FIFO Assignment for Filter 10 */
6130 #define CAN_FFA1R_FFA11 ((u16)0x0800) /* Filter FIFO Assignment for Filter 11 */
6131 #define CAN_FFA1R_FFA12 ((u16)0x1000) /* Filter FIFO Assignment for Filter 12 */
6132 #define CAN_FFA1R_FFA13 ((u16)0x2000) /* Filter FIFO Assignment for Filter 13 */
6133 
6134 
6135 /******************* Bit definition for CAN_FA1R register *******************/
6136 #define CAN_FA1R_FACT ((u16)0x3FFF) /* Filter Active */
6137 #define CAN_FA1R_FACT0 ((u16)0x0001) /* Filter 0 Active */
6138 #define CAN_FA1R_FACT1 ((u16)0x0002) /* Filter 1 Active */
6139 #define CAN_FA1R_FACT2 ((u16)0x0004) /* Filter 2 Active */
6140 #define CAN_FA1R_FACT3 ((u16)0x0008) /* Filter 3 Active */
6141 #define CAN_FA1R_FACT4 ((u16)0x0010) /* Filter 4 Active */
6142 #define CAN_FA1R_FACT5 ((u16)0x0020) /* Filter 5 Active */
6143 #define CAN_FA1R_FACT6 ((u16)0x0040) /* Filter 6 Active */
6144 #define CAN_FA1R_FACT7 ((u16)0x0080) /* Filter 7 Active */
6145 #define CAN_FA1R_FACT8 ((u16)0x0100) /* Filter 8 Active */
6146 #define CAN_FA1R_FACT9 ((u16)0x0200) /* Filter 9 Active */
6147 #define CAN_FA1R_FACT10 ((u16)0x0400) /* Filter 10 Active */
6148 #define CAN_FA1R_FACT11 ((u16)0x0800) /* Filter 11 Active */
6149 #define CAN_FA1R_FACT12 ((u16)0x1000) /* Filter 12 Active */
6150 #define CAN_FA1R_FACT13 ((u16)0x2000) /* Filter 13 Active */
6151 
6152 
6153 /******************* Bit definition for CAN_F0R1 register *******************/
6154 #define CAN_F0R1_FB0 ((u32)0x00000001) /* Filter bit 0 */
6155 #define CAN_F0R1_FB1 ((u32)0x00000002) /* Filter bit 1 */
6156 #define CAN_F0R1_FB2 ((u32)0x00000004) /* Filter bit 2 */
6157 #define CAN_F0R1_FB3 ((u32)0x00000008) /* Filter bit 3 */
6158 #define CAN_F0R1_FB4 ((u32)0x00000010) /* Filter bit 4 */
6159 #define CAN_F0R1_FB5 ((u32)0x00000020) /* Filter bit 5 */
6160 #define CAN_F0R1_FB6 ((u32)0x00000040) /* Filter bit 6 */
6161 #define CAN_F0R1_FB7 ((u32)0x00000080) /* Filter bit 7 */
6162 #define CAN_F0R1_FB8 ((u32)0x00000100) /* Filter bit 8 */
6163 #define CAN_F0R1_FB9 ((u32)0x00000200) /* Filter bit 9 */
6164 #define CAN_F0R1_FB10 ((u32)0x00000400) /* Filter bit 10 */
6165 #define CAN_F0R1_FB11 ((u32)0x00000800) /* Filter bit 11 */
6166 #define CAN_F0R1_FB12 ((u32)0x00001000) /* Filter bit 12 */
6167 #define CAN_F0R1_FB13 ((u32)0x00002000) /* Filter bit 13 */
6168 #define CAN_F0R1_FB14 ((u32)0x00004000) /* Filter bit 14 */
6169 #define CAN_F0R1_FB15 ((u32)0x00008000) /* Filter bit 15 */
6170 #define CAN_F0R1_FB16 ((u32)0x00010000) /* Filter bit 16 */
6171 #define CAN_F0R1_FB17 ((u32)0x00020000) /* Filter bit 17 */
6172 #define CAN_F0R1_FB18 ((u32)0x00040000) /* Filter bit 18 */
6173 #define CAN_F0R1_FB19 ((u32)0x00080000) /* Filter bit 19 */
6174 #define CAN_F0R1_FB20 ((u32)0x00100000) /* Filter bit 20 */
6175 #define CAN_F0R1_FB21 ((u32)0x00200000) /* Filter bit 21 */
6176 #define CAN_F0R1_FB22 ((u32)0x00400000) /* Filter bit 22 */
6177 #define CAN_F0R1_FB23 ((u32)0x00800000) /* Filter bit 23 */
6178 #define CAN_F0R1_FB24 ((u32)0x01000000) /* Filter bit 24 */
6179 #define CAN_F0R1_FB25 ((u32)0x02000000) /* Filter bit 25 */
6180 #define CAN_F0R1_FB26 ((u32)0x04000000) /* Filter bit 26 */
6181 #define CAN_F0R1_FB27 ((u32)0x08000000) /* Filter bit 27 */
6182 #define CAN_F0R1_FB28 ((u32)0x10000000) /* Filter bit 28 */
6183 #define CAN_F0R1_FB29 ((u32)0x20000000) /* Filter bit 29 */
6184 #define CAN_F0R1_FB30 ((u32)0x40000000) /* Filter bit 30 */
6185 #define CAN_F0R1_FB31 ((u32)0x80000000) /* Filter bit 31 */
6186 
6187 
6188 /******************* Bit definition for CAN_F1R1 register *******************/
6189 #define CAN_F1R1_FB0 ((u32)0x00000001) /* Filter bit 0 */
6190 #define CAN_F1R1_FB1 ((u32)0x00000002) /* Filter bit 1 */
6191 #define CAN_F1R1_FB2 ((u32)0x00000004) /* Filter bit 2 */
6192 #define CAN_F1R1_FB3 ((u32)0x00000008) /* Filter bit 3 */
6193 #define CAN_F1R1_FB4 ((u32)0x00000010) /* Filter bit 4 */
6194 #define CAN_F1R1_FB5 ((u32)0x00000020) /* Filter bit 5 */
6195 #define CAN_F1R1_FB6 ((u32)0x00000040) /* Filter bit 6 */
6196 #define CAN_F1R1_FB7 ((u32)0x00000080) /* Filter bit 7 */
6197 #define CAN_F1R1_FB8 ((u32)0x00000100) /* Filter bit 8 */
6198 #define CAN_F1R1_FB9 ((u32)0x00000200) /* Filter bit 9 */
6199 #define CAN_F1R1_FB10 ((u32)0x00000400) /* Filter bit 10 */
6200 #define CAN_F1R1_FB11 ((u32)0x00000800) /* Filter bit 11 */
6201 #define CAN_F1R1_FB12 ((u32)0x00001000) /* Filter bit 12 */
6202 #define CAN_F1R1_FB13 ((u32)0x00002000) /* Filter bit 13 */
6203 #define CAN_F1R1_FB14 ((u32)0x00004000) /* Filter bit 14 */
6204 #define CAN_F1R1_FB15 ((u32)0x00008000) /* Filter bit 15 */
6205 #define CAN_F1R1_FB16 ((u32)0x00010000) /* Filter bit 16 */
6206 #define CAN_F1R1_FB17 ((u32)0x00020000) /* Filter bit 17 */
6207 #define CAN_F1R1_FB18 ((u32)0x00040000) /* Filter bit 18 */
6208 #define CAN_F1R1_FB19 ((u32)0x00080000) /* Filter bit 19 */
6209 #define CAN_F1R1_FB20 ((u32)0x00100000) /* Filter bit 20 */
6210 #define CAN_F1R1_FB21 ((u32)0x00200000) /* Filter bit 21 */
6211 #define CAN_F1R1_FB22 ((u32)0x00400000) /* Filter bit 22 */
6212 #define CAN_F1R1_FB23 ((u32)0x00800000) /* Filter bit 23 */
6213 #define CAN_F1R1_FB24 ((u32)0x01000000) /* Filter bit 24 */
6214 #define CAN_F1R1_FB25 ((u32)0x02000000) /* Filter bit 25 */
6215 #define CAN_F1R1_FB26 ((u32)0x04000000) /* Filter bit 26 */
6216 #define CAN_F1R1_FB27 ((u32)0x08000000) /* Filter bit 27 */
6217 #define CAN_F1R1_FB28 ((u32)0x10000000) /* Filter bit 28 */
6218 #define CAN_F1R1_FB29 ((u32)0x20000000) /* Filter bit 29 */
6219 #define CAN_F1R1_FB30 ((u32)0x40000000) /* Filter bit 30 */
6220 #define CAN_F1R1_FB31 ((u32)0x80000000) /* Filter bit 31 */
6221 
6222 
6223 /******************* Bit definition for CAN_F2R1 register *******************/
6224 #define CAN_F2R1_FB0 ((u32)0x00000001) /* Filter bit 0 */
6225 #define CAN_F2R1_FB1 ((u32)0x00000002) /* Filter bit 1 */
6226 #define CAN_F2R1_FB2 ((u32)0x00000004) /* Filter bit 2 */
6227 #define CAN_F2R1_FB3 ((u32)0x00000008) /* Filter bit 3 */
6228 #define CAN_F2R1_FB4 ((u32)0x00000010) /* Filter bit 4 */
6229 #define CAN_F2R1_FB5 ((u32)0x00000020) /* Filter bit 5 */
6230 #define CAN_F2R1_FB6 ((u32)0x00000040) /* Filter bit 6 */
6231 #define CAN_F2R1_FB7 ((u32)0x00000080) /* Filter bit 7 */
6232 #define CAN_F2R1_FB8 ((u32)0x00000100) /* Filter bit 8 */
6233 #define CAN_F2R1_FB9 ((u32)0x00000200) /* Filter bit 9 */
6234 #define CAN_F2R1_FB10 ((u32)0x00000400) /* Filter bit 10 */
6235 #define CAN_F2R1_FB11 ((u32)0x00000800) /* Filter bit 11 */
6236 #define CAN_F2R1_FB12 ((u32)0x00001000) /* Filter bit 12 */
6237 #define CAN_F2R1_FB13 ((u32)0x00002000) /* Filter bit 13 */
6238 #define CAN_F2R1_FB14 ((u32)0x00004000) /* Filter bit 14 */
6239 #define CAN_F2R1_FB15 ((u32)0x00008000) /* Filter bit 15 */
6240 #define CAN_F2R1_FB16 ((u32)0x00010000) /* Filter bit 16 */
6241 #define CAN_F2R1_FB17 ((u32)0x00020000) /* Filter bit 17 */
6242 #define CAN_F2R1_FB18 ((u32)0x00040000) /* Filter bit 18 */
6243 #define CAN_F2R1_FB19 ((u32)0x00080000) /* Filter bit 19 */
6244 #define CAN_F2R1_FB20 ((u32)0x00100000) /* Filter bit 20 */
6245 #define CAN_F2R1_FB21 ((u32)0x00200000) /* Filter bit 21 */
6246 #define CAN_F2R1_FB22 ((u32)0x00400000) /* Filter bit 22 */
6247 #define CAN_F2R1_FB23 ((u32)0x00800000) /* Filter bit 23 */
6248 #define CAN_F2R1_FB24 ((u32)0x01000000) /* Filter bit 24 */
6249 #define CAN_F2R1_FB25 ((u32)0x02000000) /* Filter bit 25 */
6250 #define CAN_F2R1_FB26 ((u32)0x04000000) /* Filter bit 26 */
6251 #define CAN_F2R1_FB27 ((u32)0x08000000) /* Filter bit 27 */
6252 #define CAN_F2R1_FB28 ((u32)0x10000000) /* Filter bit 28 */
6253 #define CAN_F2R1_FB29 ((u32)0x20000000) /* Filter bit 29 */
6254 #define CAN_F2R1_FB30 ((u32)0x40000000) /* Filter bit 30 */
6255 #define CAN_F2R1_FB31 ((u32)0x80000000) /* Filter bit 31 */
6256 
6257 
6258 /******************* Bit definition for CAN_F3R1 register *******************/
6259 #define CAN_F3R1_FB0 ((u32)0x00000001) /* Filter bit 0 */
6260 #define CAN_F3R1_FB1 ((u32)0x00000002) /* Filter bit 1 */
6261 #define CAN_F3R1_FB2 ((u32)0x00000004) /* Filter bit 2 */
6262 #define CAN_F3R1_FB3 ((u32)0x00000008) /* Filter bit 3 */
6263 #define CAN_F3R1_FB4 ((u32)0x00000010) /* Filter bit 4 */
6264 #define CAN_F3R1_FB5 ((u32)0x00000020) /* Filter bit 5 */
6265 #define CAN_F3R1_FB6 ((u32)0x00000040) /* Filter bit 6 */
6266 #define CAN_F3R1_FB7 ((u32)0x00000080) /* Filter bit 7 */
6267 #define CAN_F3R1_FB8 ((u32)0x00000100) /* Filter bit 8 */
6268 #define CAN_F3R1_FB9 ((u32)0x00000200) /* Filter bit 9 */
6269 #define CAN_F3R1_FB10 ((u32)0x00000400) /* Filter bit 10 */
6270 #define CAN_F3R1_FB11 ((u32)0x00000800) /* Filter bit 11 */
6271 #define CAN_F3R1_FB12 ((u32)0x00001000) /* Filter bit 12 */
6272 #define CAN_F3R1_FB13 ((u32)0x00002000) /* Filter bit 13 */
6273 #define CAN_F3R1_FB14 ((u32)0x00004000) /* Filter bit 14 */
6274 #define CAN_F3R1_FB15 ((u32)0x00008000) /* Filter bit 15 */
6275 #define CAN_F3R1_FB16 ((u32)0x00010000) /* Filter bit 16 */
6276 #define CAN_F3R1_FB17 ((u32)0x00020000) /* Filter bit 17 */
6277 #define CAN_F3R1_FB18 ((u32)0x00040000) /* Filter bit 18 */
6278 #define CAN_F3R1_FB19 ((u32)0x00080000) /* Filter bit 19 */
6279 #define CAN_F3R1_FB20 ((u32)0x00100000) /* Filter bit 20 */
6280 #define CAN_F3R1_FB21 ((u32)0x00200000) /* Filter bit 21 */
6281 #define CAN_F3R1_FB22 ((u32)0x00400000) /* Filter bit 22 */
6282 #define CAN_F3R1_FB23 ((u32)0x00800000) /* Filter bit 23 */
6283 #define CAN_F3R1_FB24 ((u32)0x01000000) /* Filter bit 24 */
6284 #define CAN_F3R1_FB25 ((u32)0x02000000) /* Filter bit 25 */
6285 #define CAN_F3R1_FB26 ((u32)0x04000000) /* Filter bit 26 */
6286 #define CAN_F3R1_FB27 ((u32)0x08000000) /* Filter bit 27 */
6287 #define CAN_F3R1_FB28 ((u32)0x10000000) /* Filter bit 28 */
6288 #define CAN_F3R1_FB29 ((u32)0x20000000) /* Filter bit 29 */
6289 #define CAN_F3R1_FB30 ((u32)0x40000000) /* Filter bit 30 */
6290 #define CAN_F3R1_FB31 ((u32)0x80000000) /* Filter bit 31 */
6291 
6292 
6293 /******************* Bit definition for CAN_F4R1 register *******************/
6294 #define CAN_F4R1_FB0 ((u32)0x00000001) /* Filter bit 0 */
6295 #define CAN_F4R1_FB1 ((u32)0x00000002) /* Filter bit 1 */
6296 #define CAN_F4R1_FB2 ((u32)0x00000004) /* Filter bit 2 */
6297 #define CAN_F4R1_FB3 ((u32)0x00000008) /* Filter bit 3 */
6298 #define CAN_F4R1_FB4 ((u32)0x00000010) /* Filter bit 4 */
6299 #define CAN_F4R1_FB5 ((u32)0x00000020) /* Filter bit 5 */
6300 #define CAN_F4R1_FB6 ((u32)0x00000040) /* Filter bit 6 */
6301 #define CAN_F4R1_FB7 ((u32)0x00000080) /* Filter bit 7 */
6302 #define CAN_F4R1_FB8 ((u32)0x00000100) /* Filter bit 8 */
6303 #define CAN_F4R1_FB9 ((u32)0x00000200) /* Filter bit 9 */
6304 #define CAN_F4R1_FB10 ((u32)0x00000400) /* Filter bit 10 */
6305 #define CAN_F4R1_FB11 ((u32)0x00000800) /* Filter bit 11 */
6306 #define CAN_F4R1_FB12 ((u32)0x00001000) /* Filter bit 12 */
6307 #define CAN_F4R1_FB13 ((u32)0x00002000) /* Filter bit 13 */
6308 #define CAN_F4R1_FB14 ((u32)0x00004000) /* Filter bit 14 */
6309 #define CAN_F4R1_FB15 ((u32)0x00008000) /* Filter bit 15 */
6310 #define CAN_F4R1_FB16 ((u32)0x00010000) /* Filter bit 16 */
6311 #define CAN_F4R1_FB17 ((u32)0x00020000) /* Filter bit 17 */
6312 #define CAN_F4R1_FB18 ((u32)0x00040000) /* Filter bit 18 */
6313 #define CAN_F4R1_FB19 ((u32)0x00080000) /* Filter bit 19 */
6314 #define CAN_F4R1_FB20 ((u32)0x00100000) /* Filter bit 20 */
6315 #define CAN_F4R1_FB21 ((u32)0x00200000) /* Filter bit 21 */
6316 #define CAN_F4R1_FB22 ((u32)0x00400000) /* Filter bit 22 */
6317 #define CAN_F4R1_FB23 ((u32)0x00800000) /* Filter bit 23 */
6318 #define CAN_F4R1_FB24 ((u32)0x01000000) /* Filter bit 24 */
6319 #define CAN_F4R1_FB25 ((u32)0x02000000) /* Filter bit 25 */
6320 #define CAN_F4R1_FB26 ((u32)0x04000000) /* Filter bit 26 */
6321 #define CAN_F4R1_FB27 ((u32)0x08000000) /* Filter bit 27 */
6322 #define CAN_F4R1_FB28 ((u32)0x10000000) /* Filter bit 28 */
6323 #define CAN_F4R1_FB29 ((u32)0x20000000) /* Filter bit 29 */
6324 #define CAN_F4R1_FB30 ((u32)0x40000000) /* Filter bit 30 */
6325 #define CAN_F4R1_FB31 ((u32)0x80000000) /* Filter bit 31 */
6326 
6327 
6328 /******************* Bit definition for CAN_F5R1 register *******************/
6329 #define CAN_F5R1_FB0 ((u32)0x00000001) /* Filter bit 0 */
6330 #define CAN_F5R1_FB1 ((u32)0x00000002) /* Filter bit 1 */
6331 #define CAN_F5R1_FB2 ((u32)0x00000004) /* Filter bit 2 */
6332 #define CAN_F5R1_FB3 ((u32)0x00000008) /* Filter bit 3 */
6333 #define CAN_F5R1_FB4 ((u32)0x00000010) /* Filter bit 4 */
6334 #define CAN_F5R1_FB5 ((u32)0x00000020) /* Filter bit 5 */
6335 #define CAN_F5R1_FB6 ((u32)0x00000040) /* Filter bit 6 */
6336 #define CAN_F5R1_FB7 ((u32)0x00000080) /* Filter bit 7 */
6337 #define CAN_F5R1_FB8 ((u32)0x00000100) /* Filter bit 8 */
6338 #define CAN_F5R1_FB9 ((u32)0x00000200) /* Filter bit 9 */
6339 #define CAN_F5R1_FB10 ((u32)0x00000400) /* Filter bit 10 */
6340 #define CAN_F5R1_FB11 ((u32)0x00000800) /* Filter bit 11 */
6341 #define CAN_F5R1_FB12 ((u32)0x00001000) /* Filter bit 12 */
6342 #define CAN_F5R1_FB13 ((u32)0x00002000) /* Filter bit 13 */
6343 #define CAN_F5R1_FB14 ((u32)0x00004000) /* Filter bit 14 */
6344 #define CAN_F5R1_FB15 ((u32)0x00008000) /* Filter bit 15 */
6345 #define CAN_F5R1_FB16 ((u32)0x00010000) /* Filter bit 16 */
6346 #define CAN_F5R1_FB17 ((u32)0x00020000) /* Filter bit 17 */
6347 #define CAN_F5R1_FB18 ((u32)0x00040000) /* Filter bit 18 */
6348 #define CAN_F5R1_FB19 ((u32)0x00080000) /* Filter bit 19 */
6349 #define CAN_F5R1_FB20 ((u32)0x00100000) /* Filter bit 20 */
6350 #define CAN_F5R1_FB21 ((u32)0x00200000) /* Filter bit 21 */
6351 #define CAN_F5R1_FB22 ((u32)0x00400000) /* Filter bit 22 */
6352 #define CAN_F5R1_FB23 ((u32)0x00800000) /* Filter bit 23 */
6353 #define CAN_F5R1_FB24 ((u32)0x01000000) /* Filter bit 24 */
6354 #define CAN_F5R1_FB25 ((u32)0x02000000) /* Filter bit 25 */
6355 #define CAN_F5R1_FB26 ((u32)0x04000000) /* Filter bit 26 */
6356 #define CAN_F5R1_FB27 ((u32)0x08000000) /* Filter bit 27 */
6357 #define CAN_F5R1_FB28 ((u32)0x10000000) /* Filter bit 28 */
6358 #define CAN_F5R1_FB29 ((u32)0x20000000) /* Filter bit 29 */
6359 #define CAN_F5R1_FB30 ((u32)0x40000000) /* Filter bit 30 */
6360 #define CAN_F5R1_FB31 ((u32)0x80000000) /* Filter bit 31 */
6361 
6362 
6363 /******************* Bit definition for CAN_F6R1 register *******************/
6364 #define CAN_F6R1_FB0 ((u32)0x00000001) /* Filter bit 0 */
6365 #define CAN_F6R1_FB1 ((u32)0x00000002) /* Filter bit 1 */
6366 #define CAN_F6R1_FB2 ((u32)0x00000004) /* Filter bit 2 */
6367 #define CAN_F6R1_FB3 ((u32)0x00000008) /* Filter bit 3 */
6368 #define CAN_F6R1_FB4 ((u32)0x00000010) /* Filter bit 4 */
6369 #define CAN_F6R1_FB5 ((u32)0x00000020) /* Filter bit 5 */
6370 #define CAN_F6R1_FB6 ((u32)0x00000040) /* Filter bit 6 */
6371 #define CAN_F6R1_FB7 ((u32)0x00000080) /* Filter bit 7 */
6372 #define CAN_F6R1_FB8 ((u32)0x00000100) /* Filter bit 8 */
6373 #define CAN_F6R1_FB9 ((u32)0x00000200) /* Filter bit 9 */
6374 #define CAN_F6R1_FB10 ((u32)0x00000400) /* Filter bit 10 */
6375 #define CAN_F6R1_FB11 ((u32)0x00000800) /* Filter bit 11 */
6376 #define CAN_F6R1_FB12 ((u32)0x00001000) /* Filter bit 12 */
6377 #define CAN_F6R1_FB13 ((u32)0x00002000) /* Filter bit 13 */
6378 #define CAN_F6R1_FB14 ((u32)0x00004000) /* Filter bit 14 */
6379 #define CAN_F6R1_FB15 ((u32)0x00008000) /* Filter bit 15 */
6380 #define CAN_F6R1_FB16 ((u32)0x00010000) /* Filter bit 16 */
6381 #define CAN_F6R1_FB17 ((u32)0x00020000) /* Filter bit 17 */
6382 #define CAN_F6R1_FB18 ((u32)0x00040000) /* Filter bit 18 */
6383 #define CAN_F6R1_FB19 ((u32)0x00080000) /* Filter bit 19 */
6384 #define CAN_F6R1_FB20 ((u32)0x00100000) /* Filter bit 20 */
6385 #define CAN_F6R1_FB21 ((u32)0x00200000) /* Filter bit 21 */
6386 #define CAN_F6R1_FB22 ((u32)0x00400000) /* Filter bit 22 */
6387 #define CAN_F6R1_FB23 ((u32)0x00800000) /* Filter bit 23 */
6388 #define CAN_F6R1_FB24 ((u32)0x01000000) /* Filter bit 24 */
6389 #define CAN_F6R1_FB25 ((u32)0x02000000) /* Filter bit 25 */
6390 #define CAN_F6R1_FB26 ((u32)0x04000000) /* Filter bit 26 */
6391 #define CAN_F6R1_FB27 ((u32)0x08000000) /* Filter bit 27 */
6392 #define CAN_F6R1_FB28 ((u32)0x10000000) /* Filter bit 28 */
6393 #define CAN_F6R1_FB29 ((u32)0x20000000) /* Filter bit 29 */
6394 #define CAN_F6R1_FB30 ((u32)0x40000000) /* Filter bit 30 */
6395 #define CAN_F6R1_FB31 ((u32)0x80000000) /* Filter bit 31 */
6396 
6397 
6398 /******************* Bit definition for CAN_F7R1 register *******************/
6399 #define CAN_F7R1_FB0 ((u32)0x00000001) /* Filter bit 0 */
6400 #define CAN_F7R1_FB1 ((u32)0x00000002) /* Filter bit 1 */
6401 #define CAN_F7R1_FB2 ((u32)0x00000004) /* Filter bit 2 */
6402 #define CAN_F7R1_FB3 ((u32)0x00000008) /* Filter bit 3 */
6403 #define CAN_F7R1_FB4 ((u32)0x00000010) /* Filter bit 4 */
6404 #define CAN_F7R1_FB5 ((u32)0x00000020) /* Filter bit 5 */
6405 #define CAN_F7R1_FB6 ((u32)0x00000040) /* Filter bit 6 */
6406 #define CAN_F7R1_FB7 ((u32)0x00000080) /* Filter bit 7 */
6407 #define CAN_F7R1_FB8 ((u32)0x00000100) /* Filter bit 8 */
6408 #define CAN_F7R1_FB9 ((u32)0x00000200) /* Filter bit 9 */
6409 #define CAN_F7R1_FB10 ((u32)0x00000400) /* Filter bit 10 */
6410 #define CAN_F7R1_FB11 ((u32)0x00000800) /* Filter bit 11 */
6411 #define CAN_F7R1_FB12 ((u32)0x00001000) /* Filter bit 12 */
6412 #define CAN_F7R1_FB13 ((u32)0x00002000) /* Filter bit 13 */
6413 #define CAN_F7R1_FB14 ((u32)0x00004000) /* Filter bit 14 */
6414 #define CAN_F7R1_FB15 ((u32)0x00008000) /* Filter bit 15 */
6415 #define CAN_F7R1_FB16 ((u32)0x00010000) /* Filter bit 16 */
6416 #define CAN_F7R1_FB17 ((u32)0x00020000) /* Filter bit 17 */
6417 #define CAN_F7R1_FB18 ((u32)0x00040000) /* Filter bit 18 */
6418 #define CAN_F7R1_FB19 ((u32)0x00080000) /* Filter bit 19 */
6419 #define CAN_F7R1_FB20 ((u32)0x00100000) /* Filter bit 20 */
6420 #define CAN_F7R1_FB21 ((u32)0x00200000) /* Filter bit 21 */
6421 #define CAN_F7R1_FB22 ((u32)0x00400000) /* Filter bit 22 */
6422 #define CAN_F7R1_FB23 ((u32)0x00800000) /* Filter bit 23 */
6423 #define CAN_F7R1_FB24 ((u32)0x01000000) /* Filter bit 24 */
6424 #define CAN_F7R1_FB25 ((u32)0x02000000) /* Filter bit 25 */
6425 #define CAN_F7R1_FB26 ((u32)0x04000000) /* Filter bit 26 */
6426 #define CAN_F7R1_FB27 ((u32)0x08000000) /* Filter bit 27 */
6427 #define CAN_F7R1_FB28 ((u32)0x10000000) /* Filter bit 28 */
6428 #define CAN_F7R1_FB29 ((u32)0x20000000) /* Filter bit 29 */
6429 #define CAN_F7R1_FB30 ((u32)0x40000000) /* Filter bit 30 */
6430 #define CAN_F7R1_FB31 ((u32)0x80000000) /* Filter bit 31 */
6431 
6432 
6433 /******************* Bit definition for CAN_F8R1 register *******************/
6434 #define CAN_F8R1_FB0 ((u32)0x00000001) /* Filter bit 0 */
6435 #define CAN_F8R1_FB1 ((u32)0x00000002) /* Filter bit 1 */
6436 #define CAN_F8R1_FB2 ((u32)0x00000004) /* Filter bit 2 */
6437 #define CAN_F8R1_FB3 ((u32)0x00000008) /* Filter bit 3 */
6438 #define CAN_F8R1_FB4 ((u32)0x00000010) /* Filter bit 4 */
6439 #define CAN_F8R1_FB5 ((u32)0x00000020) /* Filter bit 5 */
6440 #define CAN_F8R1_FB6 ((u32)0x00000040) /* Filter bit 6 */
6441 #define CAN_F8R1_FB7 ((u32)0x00000080) /* Filter bit 7 */
6442 #define CAN_F8R1_FB8 ((u32)0x00000100) /* Filter bit 8 */
6443 #define CAN_F8R1_FB9 ((u32)0x00000200) /* Filter bit 9 */
6444 #define CAN_F8R1_FB10 ((u32)0x00000400) /* Filter bit 10 */
6445 #define CAN_F8R1_FB11 ((u32)0x00000800) /* Filter bit 11 */
6446 #define CAN_F8R1_FB12 ((u32)0x00001000) /* Filter bit 12 */
6447 #define CAN_F8R1_FB13 ((u32)0x00002000) /* Filter bit 13 */
6448 #define CAN_F8R1_FB14 ((u32)0x00004000) /* Filter bit 14 */
6449 #define CAN_F8R1_FB15 ((u32)0x00008000) /* Filter bit 15 */
6450 #define CAN_F8R1_FB16 ((u32)0x00010000) /* Filter bit 16 */
6451 #define CAN_F8R1_FB17 ((u32)0x00020000) /* Filter bit 17 */
6452 #define CAN_F8R1_FB18 ((u32)0x00040000) /* Filter bit 18 */
6453 #define CAN_F8R1_FB19 ((u32)0x00080000) /* Filter bit 19 */
6454 #define CAN_F8R1_FB20 ((u32)0x00100000) /* Filter bit 20 */
6455 #define CAN_F8R1_FB21 ((u32)0x00200000) /* Filter bit 21 */
6456 #define CAN_F8R1_FB22 ((u32)0x00400000) /* Filter bit 22 */
6457 #define CAN_F8R1_FB23 ((u32)0x00800000) /* Filter bit 23 */
6458 #define CAN_F8R1_FB24 ((u32)0x01000000) /* Filter bit 24 */
6459 #define CAN_F8R1_FB25 ((u32)0x02000000) /* Filter bit 25 */
6460 #define CAN_F8R1_FB26 ((u32)0x04000000) /* Filter bit 26 */
6461 #define CAN_F8R1_FB27 ((u32)0x08000000) /* Filter bit 27 */
6462 #define CAN_F8R1_FB28 ((u32)0x10000000) /* Filter bit 28 */
6463 #define CAN_F8R1_FB29 ((u32)0x20000000) /* Filter bit 29 */
6464 #define CAN_F8R1_FB30 ((u32)0x40000000) /* Filter bit 30 */
6465 #define CAN_F8R1_FB31 ((u32)0x80000000) /* Filter bit 31 */
6466 
6467 
6468 /******************* Bit definition for CAN_F9R1 register *******************/
6469 #define CAN_F9R1_FB0 ((u32)0x00000001) /* Filter bit 0 */
6470 #define CAN_F9R1_FB1 ((u32)0x00000002) /* Filter bit 1 */
6471 #define CAN_F9R1_FB2 ((u32)0x00000004) /* Filter bit 2 */
6472 #define CAN_F9R1_FB3 ((u32)0x00000008) /* Filter bit 3 */
6473 #define CAN_F9R1_FB4 ((u32)0x00000010) /* Filter bit 4 */
6474 #define CAN_F9R1_FB5 ((u32)0x00000020) /* Filter bit 5 */
6475 #define CAN_F9R1_FB6 ((u32)0x00000040) /* Filter bit 6 */
6476 #define CAN_F9R1_FB7 ((u32)0x00000080) /* Filter bit 7 */
6477 #define CAN_F9R1_FB8 ((u32)0x00000100) /* Filter bit 8 */
6478 #define CAN_F9R1_FB9 ((u32)0x00000200) /* Filter bit 9 */
6479 #define CAN_F9R1_FB10 ((u32)0x00000400) /* Filter bit 10 */
6480 #define CAN_F9R1_FB11 ((u32)0x00000800) /* Filter bit 11 */
6481 #define CAN_F9R1_FB12 ((u32)0x00001000) /* Filter bit 12 */
6482 #define CAN_F9R1_FB13 ((u32)0x00002000) /* Filter bit 13 */
6483 #define CAN_F9R1_FB14 ((u32)0x00004000) /* Filter bit 14 */
6484 #define CAN_F9R1_FB15 ((u32)0x00008000) /* Filter bit 15 */
6485 #define CAN_F9R1_FB16 ((u32)0x00010000) /* Filter bit 16 */
6486 #define CAN_F9R1_FB17 ((u32)0x00020000) /* Filter bit 17 */
6487 #define CAN_F9R1_FB18 ((u32)0x00040000) /* Filter bit 18 */
6488 #define CAN_F9R1_FB19 ((u32)0x00080000) /* Filter bit 19 */
6489 #define CAN_F9R1_FB20 ((u32)0x00100000) /* Filter bit 20 */
6490 #define CAN_F9R1_FB21 ((u32)0x00200000) /* Filter bit 21 */
6491 #define CAN_F9R1_FB22 ((u32)0x00400000) /* Filter bit 22 */
6492 #define CAN_F9R1_FB23 ((u32)0x00800000) /* Filter bit 23 */
6493 #define CAN_F9R1_FB24 ((u32)0x01000000) /* Filter bit 24 */
6494 #define CAN_F9R1_FB25 ((u32)0x02000000) /* Filter bit 25 */
6495 #define CAN_F9R1_FB26 ((u32)0x04000000) /* Filter bit 26 */
6496 #define CAN_F9R1_FB27 ((u32)0x08000000) /* Filter bit 27 */
6497 #define CAN_F9R1_FB28 ((u32)0x10000000) /* Filter bit 28 */
6498 #define CAN_F9R1_FB29 ((u32)0x20000000) /* Filter bit 29 */
6499 #define CAN_F9R1_FB30 ((u32)0x40000000) /* Filter bit 30 */
6500 #define CAN_F9R1_FB31 ((u32)0x80000000) /* Filter bit 31 */
6501 
6502 
6503 /******************* Bit definition for CAN_F10R1 register ******************/
6504 #define CAN_F10R1_FB0 ((u32)0x00000001) /* Filter bit 0 */
6505 #define CAN_F10R1_FB1 ((u32)0x00000002) /* Filter bit 1 */
6506 #define CAN_F10R1_FB2 ((u32)0x00000004) /* Filter bit 2 */
6507 #define CAN_F10R1_FB3 ((u32)0x00000008) /* Filter bit 3 */
6508 #define CAN_F10R1_FB4 ((u32)0x00000010) /* Filter bit 4 */
6509 #define CAN_F10R1_FB5 ((u32)0x00000020) /* Filter bit 5 */
6510 #define CAN_F10R1_FB6 ((u32)0x00000040) /* Filter bit 6 */
6511 #define CAN_F10R1_FB7 ((u32)0x00000080) /* Filter bit 7 */
6512 #define CAN_F10R1_FB8 ((u32)0x00000100) /* Filter bit 8 */
6513 #define CAN_F10R1_FB9 ((u32)0x00000200) /* Filter bit 9 */
6514 #define CAN_F10R1_FB10 ((u32)0x00000400) /* Filter bit 10 */
6515 #define CAN_F10R1_FB11 ((u32)0x00000800) /* Filter bit 11 */
6516 #define CAN_F10R1_FB12 ((u32)0x00001000) /* Filter bit 12 */
6517 #define CAN_F10R1_FB13 ((u32)0x00002000) /* Filter bit 13 */
6518 #define CAN_F10R1_FB14 ((u32)0x00004000) /* Filter bit 14 */
6519 #define CAN_F10R1_FB15 ((u32)0x00008000) /* Filter bit 15 */
6520 #define CAN_F10R1_FB16 ((u32)0x00010000) /* Filter bit 16 */
6521 #define CAN_F10R1_FB17 ((u32)0x00020000) /* Filter bit 17 */
6522 #define CAN_F10R1_FB18 ((u32)0x00040000) /* Filter bit 18 */
6523 #define CAN_F10R1_FB19 ((u32)0x00080000) /* Filter bit 19 */
6524 #define CAN_F10R1_FB20 ((u32)0x00100000) /* Filter bit 20 */
6525 #define CAN_F10R1_FB21 ((u32)0x00200000) /* Filter bit 21 */
6526 #define CAN_F10R1_FB22 ((u32)0x00400000) /* Filter bit 22 */
6527 #define CAN_F10R1_FB23 ((u32)0x00800000) /* Filter bit 23 */
6528 #define CAN_F10R1_FB24 ((u32)0x01000000) /* Filter bit 24 */
6529 #define CAN_F10R1_FB25 ((u32)0x02000000) /* Filter bit 25 */
6530 #define CAN_F10R1_FB26 ((u32)0x04000000) /* Filter bit 26 */
6531 #define CAN_F10R1_FB27 ((u32)0x08000000) /* Filter bit 27 */
6532 #define CAN_F10R1_FB28 ((u32)0x10000000) /* Filter bit 28 */
6533 #define CAN_F10R1_FB29 ((u32)0x20000000) /* Filter bit 29 */
6534 #define CAN_F10R1_FB30 ((u32)0x40000000) /* Filter bit 30 */
6535 #define CAN_F10R1_FB31 ((u32)0x80000000) /* Filter bit 31 */
6536 
6537 
6538 /******************* Bit definition for CAN_F11R1 register ******************/
6539 #define CAN_F11R1_FB0 ((u32)0x00000001) /* Filter bit 0 */
6540 #define CAN_F11R1_FB1 ((u32)0x00000002) /* Filter bit 1 */
6541 #define CAN_F11R1_FB2 ((u32)0x00000004) /* Filter bit 2 */
6542 #define CAN_F11R1_FB3 ((u32)0x00000008) /* Filter bit 3 */
6543 #define CAN_F11R1_FB4 ((u32)0x00000010) /* Filter bit 4 */
6544 #define CAN_F11R1_FB5 ((u32)0x00000020) /* Filter bit 5 */
6545 #define CAN_F11R1_FB6 ((u32)0x00000040) /* Filter bit 6 */
6546 #define CAN_F11R1_FB7 ((u32)0x00000080) /* Filter bit 7 */
6547 #define CAN_F11R1_FB8 ((u32)0x00000100) /* Filter bit 8 */
6548 #define CAN_F11R1_FB9 ((u32)0x00000200) /* Filter bit 9 */
6549 #define CAN_F11R1_FB10 ((u32)0x00000400) /* Filter bit 10 */
6550 #define CAN_F11R1_FB11 ((u32)0x00000800) /* Filter bit 11 */
6551 #define CAN_F11R1_FB12 ((u32)0x00001000) /* Filter bit 12 */
6552 #define CAN_F11R1_FB13 ((u32)0x00002000) /* Filter bit 13 */
6553 #define CAN_F11R1_FB14 ((u32)0x00004000) /* Filter bit 14 */
6554 #define CAN_F11R1_FB15 ((u32)0x00008000) /* Filter bit 15 */
6555 #define CAN_F11R1_FB16 ((u32)0x00010000) /* Filter bit 16 */
6556 #define CAN_F11R1_FB17 ((u32)0x00020000) /* Filter bit 17 */
6557 #define CAN_F11R1_FB18 ((u32)0x00040000) /* Filter bit 18 */
6558 #define CAN_F11R1_FB19 ((u32)0x00080000) /* Filter bit 19 */
6559 #define CAN_F11R1_FB20 ((u32)0x00100000) /* Filter bit 20 */
6560 #define CAN_F11R1_FB21 ((u32)0x00200000) /* Filter bit 21 */
6561 #define CAN_F11R1_FB22 ((u32)0x00400000) /* Filter bit 22 */
6562 #define CAN_F11R1_FB23 ((u32)0x00800000) /* Filter bit 23 */
6563 #define CAN_F11R1_FB24 ((u32)0x01000000) /* Filter bit 24 */
6564 #define CAN_F11R1_FB25 ((u32)0x02000000) /* Filter bit 25 */
6565 #define CAN_F11R1_FB26 ((u32)0x04000000) /* Filter bit 26 */
6566 #define CAN_F11R1_FB27 ((u32)0x08000000) /* Filter bit 27 */
6567 #define CAN_F11R1_FB28 ((u32)0x10000000) /* Filter bit 28 */
6568 #define CAN_F11R1_FB29 ((u32)0x20000000) /* Filter bit 29 */
6569 #define CAN_F11R1_FB30 ((u32)0x40000000) /* Filter bit 30 */
6570 #define CAN_F11R1_FB31 ((u32)0x80000000) /* Filter bit 31 */
6571 
6572 
6573 /******************* Bit definition for CAN_F12R1 register ******************/
6574 #define CAN_F12R1_FB0 ((u32)0x00000001) /* Filter bit 0 */
6575 #define CAN_F12R1_FB1 ((u32)0x00000002) /* Filter bit 1 */
6576 #define CAN_F12R1_FB2 ((u32)0x00000004) /* Filter bit 2 */
6577 #define CAN_F12R1_FB3 ((u32)0x00000008) /* Filter bit 3 */
6578 #define CAN_F12R1_FB4 ((u32)0x00000010) /* Filter bit 4 */
6579 #define CAN_F12R1_FB5 ((u32)0x00000020) /* Filter bit 5 */
6580 #define CAN_F12R1_FB6 ((u32)0x00000040) /* Filter bit 6 */
6581 #define CAN_F12R1_FB7 ((u32)0x00000080) /* Filter bit 7 */
6582 #define CAN_F12R1_FB8 ((u32)0x00000100) /* Filter bit 8 */
6583 #define CAN_F12R1_FB9 ((u32)0x00000200) /* Filter bit 9 */
6584 #define CAN_F12R1_FB10 ((u32)0x00000400) /* Filter bit 10 */
6585 #define CAN_F12R1_FB11 ((u32)0x00000800) /* Filter bit 11 */
6586 #define CAN_F12R1_FB12 ((u32)0x00001000) /* Filter bit 12 */
6587 #define CAN_F12R1_FB13 ((u32)0x00002000) /* Filter bit 13 */
6588 #define CAN_F12R1_FB14 ((u32)0x00004000) /* Filter bit 14 */
6589 #define CAN_F12R1_FB15 ((u32)0x00008000) /* Filter bit 15 */
6590 #define CAN_F12R1_FB16 ((u32)0x00010000) /* Filter bit 16 */
6591 #define CAN_F12R1_FB17 ((u32)0x00020000) /* Filter bit 17 */
6592 #define CAN_F12R1_FB18 ((u32)0x00040000) /* Filter bit 18 */
6593 #define CAN_F12R1_FB19 ((u32)0x00080000) /* Filter bit 19 */
6594 #define CAN_F12R1_FB20 ((u32)0x00100000) /* Filter bit 20 */
6595 #define CAN_F12R1_FB21 ((u32)0x00200000) /* Filter bit 21 */
6596 #define CAN_F12R1_FB22 ((u32)0x00400000) /* Filter bit 22 */
6597 #define CAN_F12R1_FB23 ((u32)0x00800000) /* Filter bit 23 */
6598 #define CAN_F12R1_FB24 ((u32)0x01000000) /* Filter bit 24 */
6599 #define CAN_F12R1_FB25 ((u32)0x02000000) /* Filter bit 25 */
6600 #define CAN_F12R1_FB26 ((u32)0x04000000) /* Filter bit 26 */
6601 #define CAN_F12R1_FB27 ((u32)0x08000000) /* Filter bit 27 */
6602 #define CAN_F12R1_FB28 ((u32)0x10000000) /* Filter bit 28 */
6603 #define CAN_F12R1_FB29 ((u32)0x20000000) /* Filter bit 29 */
6604 #define CAN_F12R1_FB30 ((u32)0x40000000) /* Filter bit 30 */
6605 #define CAN_F12R1_FB31 ((u32)0x80000000) /* Filter bit 31 */
6606 
6607 
6608 /******************* Bit definition for CAN_F13R1 register ******************/
6609 #define CAN_F13R1_FB0 ((u32)0x00000001) /* Filter bit 0 */
6610 #define CAN_F13R1_FB1 ((u32)0x00000002) /* Filter bit 1 */
6611 #define CAN_F13R1_FB2 ((u32)0x00000004) /* Filter bit 2 */
6612 #define CAN_F13R1_FB3 ((u32)0x00000008) /* Filter bit 3 */
6613 #define CAN_F13R1_FB4 ((u32)0x00000010) /* Filter bit 4 */
6614 #define CAN_F13R1_FB5 ((u32)0x00000020) /* Filter bit 5 */
6615 #define CAN_F13R1_FB6 ((u32)0x00000040) /* Filter bit 6 */
6616 #define CAN_F13R1_FB7 ((u32)0x00000080) /* Filter bit 7 */
6617 #define CAN_F13R1_FB8 ((u32)0x00000100) /* Filter bit 8 */
6618 #define CAN_F13R1_FB9 ((u32)0x00000200) /* Filter bit 9 */
6619 #define CAN_F13R1_FB10 ((u32)0x00000400) /* Filter bit 10 */
6620 #define CAN_F13R1_FB11 ((u32)0x00000800) /* Filter bit 11 */
6621 #define CAN_F13R1_FB12 ((u32)0x00001000) /* Filter bit 12 */
6622 #define CAN_F13R1_FB13 ((u32)0x00002000) /* Filter bit 13 */
6623 #define CAN_F13R1_FB14 ((u32)0x00004000) /* Filter bit 14 */
6624 #define CAN_F13R1_FB15 ((u32)0x00008000) /* Filter bit 15 */
6625 #define CAN_F13R1_FB16 ((u32)0x00010000) /* Filter bit 16 */
6626 #define CAN_F13R1_FB17 ((u32)0x00020000) /* Filter bit 17 */
6627 #define CAN_F13R1_FB18 ((u32)0x00040000) /* Filter bit 18 */
6628 #define CAN_F13R1_FB19 ((u32)0x00080000) /* Filter bit 19 */
6629 #define CAN_F13R1_FB20 ((u32)0x00100000) /* Filter bit 20 */
6630 #define CAN_F13R1_FB21 ((u32)0x00200000) /* Filter bit 21 */
6631 #define CAN_F13R1_FB22 ((u32)0x00400000) /* Filter bit 22 */
6632 #define CAN_F13R1_FB23 ((u32)0x00800000) /* Filter bit 23 */
6633 #define CAN_F13R1_FB24 ((u32)0x01000000) /* Filter bit 24 */
6634 #define CAN_F13R1_FB25 ((u32)0x02000000) /* Filter bit 25 */
6635 #define CAN_F13R1_FB26 ((u32)0x04000000) /* Filter bit 26 */
6636 #define CAN_F13R1_FB27 ((u32)0x08000000) /* Filter bit 27 */
6637 #define CAN_F13R1_FB28 ((u32)0x10000000) /* Filter bit 28 */
6638 #define CAN_F13R1_FB29 ((u32)0x20000000) /* Filter bit 29 */
6639 #define CAN_F13R1_FB30 ((u32)0x40000000) /* Filter bit 30 */
6640 #define CAN_F13R1_FB31 ((u32)0x80000000) /* Filter bit 31 */
6641 
6642 
6643 /******************* Bit definition for CAN_F0R2 register *******************/
6644 #define CAN_F0R2_FB0 ((u32)0x00000001) /* Filter bit 0 */
6645 #define CAN_F0R2_FB1 ((u32)0x00000002) /* Filter bit 1 */
6646 #define CAN_F0R2_FB2 ((u32)0x00000004) /* Filter bit 2 */
6647 #define CAN_F0R2_FB3 ((u32)0x00000008) /* Filter bit 3 */
6648 #define CAN_F0R2_FB4 ((u32)0x00000010) /* Filter bit 4 */
6649 #define CAN_F0R2_FB5 ((u32)0x00000020) /* Filter bit 5 */
6650 #define CAN_F0R2_FB6 ((u32)0x00000040) /* Filter bit 6 */
6651 #define CAN_F0R2_FB7 ((u32)0x00000080) /* Filter bit 7 */
6652 #define CAN_F0R2_FB8 ((u32)0x00000100) /* Filter bit 8 */
6653 #define CAN_F0R2_FB9 ((u32)0x00000200) /* Filter bit 9 */
6654 #define CAN_F0R2_FB10 ((u32)0x00000400) /* Filter bit 10 */
6655 #define CAN_F0R2_FB11 ((u32)0x00000800) /* Filter bit 11 */
6656 #define CAN_F0R2_FB12 ((u32)0x00001000) /* Filter bit 12 */
6657 #define CAN_F0R2_FB13 ((u32)0x00002000) /* Filter bit 13 */
6658 #define CAN_F0R2_FB14 ((u32)0x00004000) /* Filter bit 14 */
6659 #define CAN_F0R2_FB15 ((u32)0x00008000) /* Filter bit 15 */
6660 #define CAN_F0R2_FB16 ((u32)0x00010000) /* Filter bit 16 */
6661 #define CAN_F0R2_FB17 ((u32)0x00020000) /* Filter bit 17 */
6662 #define CAN_F0R2_FB18 ((u32)0x00040000) /* Filter bit 18 */
6663 #define CAN_F0R2_FB19 ((u32)0x00080000) /* Filter bit 19 */
6664 #define CAN_F0R2_FB20 ((u32)0x00100000) /* Filter bit 20 */
6665 #define CAN_F0R2_FB21 ((u32)0x00200000) /* Filter bit 21 */
6666 #define CAN_F0R2_FB22 ((u32)0x00400000) /* Filter bit 22 */
6667 #define CAN_F0R2_FB23 ((u32)0x00800000) /* Filter bit 23 */
6668 #define CAN_F0R2_FB24 ((u32)0x01000000) /* Filter bit 24 */
6669 #define CAN_F0R2_FB25 ((u32)0x02000000) /* Filter bit 25 */
6670 #define CAN_F0R2_FB26 ((u32)0x04000000) /* Filter bit 26 */
6671 #define CAN_F0R2_FB27 ((u32)0x08000000) /* Filter bit 27 */
6672 #define CAN_F0R2_FB28 ((u32)0x10000000) /* Filter bit 28 */
6673 #define CAN_F0R2_FB29 ((u32)0x20000000) /* Filter bit 29 */
6674 #define CAN_F0R2_FB30 ((u32)0x40000000) /* Filter bit 30 */
6675 #define CAN_F0R2_FB31 ((u32)0x80000000) /* Filter bit 31 */
6676 
6677 
6678 /******************* Bit definition for CAN_F1R2 register *******************/
6679 #define CAN_F1R2_FB0 ((u32)0x00000001) /* Filter bit 0 */
6680 #define CAN_F1R2_FB1 ((u32)0x00000002) /* Filter bit 1 */
6681 #define CAN_F1R2_FB2 ((u32)0x00000004) /* Filter bit 2 */
6682 #define CAN_F1R2_FB3 ((u32)0x00000008) /* Filter bit 3 */
6683 #define CAN_F1R2_FB4 ((u32)0x00000010) /* Filter bit 4 */
6684 #define CAN_F1R2_FB5 ((u32)0x00000020) /* Filter bit 5 */
6685 #define CAN_F1R2_FB6 ((u32)0x00000040) /* Filter bit 6 */
6686 #define CAN_F1R2_FB7 ((u32)0x00000080) /* Filter bit 7 */
6687 #define CAN_F1R2_FB8 ((u32)0x00000100) /* Filter bit 8 */
6688 #define CAN_F1R2_FB9 ((u32)0x00000200) /* Filter bit 9 */
6689 #define CAN_F1R2_FB10 ((u32)0x00000400) /* Filter bit 10 */
6690 #define CAN_F1R2_FB11 ((u32)0x00000800) /* Filter bit 11 */
6691 #define CAN_F1R2_FB12 ((u32)0x00001000) /* Filter bit 12 */
6692 #define CAN_F1R2_FB13 ((u32)0x00002000) /* Filter bit 13 */
6693 #define CAN_F1R2_FB14 ((u32)0x00004000) /* Filter bit 14 */
6694 #define CAN_F1R2_FB15 ((u32)0x00008000) /* Filter bit 15 */
6695 #define CAN_F1R2_FB16 ((u32)0x00010000) /* Filter bit 16 */
6696 #define CAN_F1R2_FB17 ((u32)0x00020000) /* Filter bit 17 */
6697 #define CAN_F1R2_FB18 ((u32)0x00040000) /* Filter bit 18 */
6698 #define CAN_F1R2_FB19 ((u32)0x00080000) /* Filter bit 19 */
6699 #define CAN_F1R2_FB20 ((u32)0x00100000) /* Filter bit 20 */
6700 #define CAN_F1R2_FB21 ((u32)0x00200000) /* Filter bit 21 */
6701 #define CAN_F1R2_FB22 ((u32)0x00400000) /* Filter bit 22 */
6702 #define CAN_F1R2_FB23 ((u32)0x00800000) /* Filter bit 23 */
6703 #define CAN_F1R2_FB24 ((u32)0x01000000) /* Filter bit 24 */
6704 #define CAN_F1R2_FB25 ((u32)0x02000000) /* Filter bit 25 */
6705 #define CAN_F1R2_FB26 ((u32)0x04000000) /* Filter bit 26 */
6706 #define CAN_F1R2_FB27 ((u32)0x08000000) /* Filter bit 27 */
6707 #define CAN_F1R2_FB28 ((u32)0x10000000) /* Filter bit 28 */
6708 #define CAN_F1R2_FB29 ((u32)0x20000000) /* Filter bit 29 */
6709 #define CAN_F1R2_FB30 ((u32)0x40000000) /* Filter bit 30 */
6710 #define CAN_F1R2_FB31 ((u32)0x80000000) /* Filter bit 31 */
6711 
6712 
6713 /******************* Bit definition for CAN_F2R2 register *******************/
6714 #define CAN_F2R2_FB0 ((u32)0x00000001) /* Filter bit 0 */
6715 #define CAN_F2R2_FB1 ((u32)0x00000002) /* Filter bit 1 */
6716 #define CAN_F2R2_FB2 ((u32)0x00000004) /* Filter bit 2 */
6717 #define CAN_F2R2_FB3 ((u32)0x00000008) /* Filter bit 3 */
6718 #define CAN_F2R2_FB4 ((u32)0x00000010) /* Filter bit 4 */
6719 #define CAN_F2R2_FB5 ((u32)0x00000020) /* Filter bit 5 */
6720 #define CAN_F2R2_FB6 ((u32)0x00000040) /* Filter bit 6 */
6721 #define CAN_F2R2_FB7 ((u32)0x00000080) /* Filter bit 7 */
6722 #define CAN_F2R2_FB8 ((u32)0x00000100) /* Filter bit 8 */
6723 #define CAN_F2R2_FB9 ((u32)0x00000200) /* Filter bit 9 */
6724 #define CAN_F2R2_FB10 ((u32)0x00000400) /* Filter bit 10 */
6725 #define CAN_F2R2_FB11 ((u32)0x00000800) /* Filter bit 11 */
6726 #define CAN_F2R2_FB12 ((u32)0x00001000) /* Filter bit 12 */
6727 #define CAN_F2R2_FB13 ((u32)0x00002000) /* Filter bit 13 */
6728 #define CAN_F2R2_FB14 ((u32)0x00004000) /* Filter bit 14 */
6729 #define CAN_F2R2_FB15 ((u32)0x00008000) /* Filter bit 15 */
6730 #define CAN_F2R2_FB16 ((u32)0x00010000) /* Filter bit 16 */
6731 #define CAN_F2R2_FB17 ((u32)0x00020000) /* Filter bit 17 */
6732 #define CAN_F2R2_FB18 ((u32)0x00040000) /* Filter bit 18 */
6733 #define CAN_F2R2_FB19 ((u32)0x00080000) /* Filter bit 19 */
6734 #define CAN_F2R2_FB20 ((u32)0x00100000) /* Filter bit 20 */
6735 #define CAN_F2R2_FB21 ((u32)0x00200000) /* Filter bit 21 */
6736 #define CAN_F2R2_FB22 ((u32)0x00400000) /* Filter bit 22 */
6737 #define CAN_F2R2_FB23 ((u32)0x00800000) /* Filter bit 23 */
6738 #define CAN_F2R2_FB24 ((u32)0x01000000) /* Filter bit 24 */
6739 #define CAN_F2R2_FB25 ((u32)0x02000000) /* Filter bit 25 */
6740 #define CAN_F2R2_FB26 ((u32)0x04000000) /* Filter bit 26 */
6741 #define CAN_F2R2_FB27 ((u32)0x08000000) /* Filter bit 27 */
6742 #define CAN_F2R2_FB28 ((u32)0x10000000) /* Filter bit 28 */
6743 #define CAN_F2R2_FB29 ((u32)0x20000000) /* Filter bit 29 */
6744 #define CAN_F2R2_FB30 ((u32)0x40000000) /* Filter bit 30 */
6745 #define CAN_F2R2_FB31 ((u32)0x80000000) /* Filter bit 31 */
6746 
6747 
6748 /******************* Bit definition for CAN_F3R2 register *******************/
6749 #define CAN_F3R2_FB0 ((u32)0x00000001) /* Filter bit 0 */
6750 #define CAN_F3R2_FB1 ((u32)0x00000002) /* Filter bit 1 */
6751 #define CAN_F3R2_FB2 ((u32)0x00000004) /* Filter bit 2 */
6752 #define CAN_F3R2_FB3 ((u32)0x00000008) /* Filter bit 3 */
6753 #define CAN_F3R2_FB4 ((u32)0x00000010) /* Filter bit 4 */
6754 #define CAN_F3R2_FB5 ((u32)0x00000020) /* Filter bit 5 */
6755 #define CAN_F3R2_FB6 ((u32)0x00000040) /* Filter bit 6 */
6756 #define CAN_F3R2_FB7 ((u32)0x00000080) /* Filter bit 7 */
6757 #define CAN_F3R2_FB8 ((u32)0x00000100) /* Filter bit 8 */
6758 #define CAN_F3R2_FB9 ((u32)0x00000200) /* Filter bit 9 */
6759 #define CAN_F3R2_FB10 ((u32)0x00000400) /* Filter bit 10 */
6760 #define CAN_F3R2_FB11 ((u32)0x00000800) /* Filter bit 11 */
6761 #define CAN_F3R2_FB12 ((u32)0x00001000) /* Filter bit 12 */
6762 #define CAN_F3R2_FB13 ((u32)0x00002000) /* Filter bit 13 */
6763 #define CAN_F3R2_FB14 ((u32)0x00004000) /* Filter bit 14 */
6764 #define CAN_F3R2_FB15 ((u32)0x00008000) /* Filter bit 15 */
6765 #define CAN_F3R2_FB16 ((u32)0x00010000) /* Filter bit 16 */
6766 #define CAN_F3R2_FB17 ((u32)0x00020000) /* Filter bit 17 */
6767 #define CAN_F3R2_FB18 ((u32)0x00040000) /* Filter bit 18 */
6768 #define CAN_F3R2_FB19 ((u32)0x00080000) /* Filter bit 19 */
6769 #define CAN_F3R2_FB20 ((u32)0x00100000) /* Filter bit 20 */
6770 #define CAN_F3R2_FB21 ((u32)0x00200000) /* Filter bit 21 */
6771 #define CAN_F3R2_FB22 ((u32)0x00400000) /* Filter bit 22 */
6772 #define CAN_F3R2_FB23 ((u32)0x00800000) /* Filter bit 23 */
6773 #define CAN_F3R2_FB24 ((u32)0x01000000) /* Filter bit 24 */
6774 #define CAN_F3R2_FB25 ((u32)0x02000000) /* Filter bit 25 */
6775 #define CAN_F3R2_FB26 ((u32)0x04000000) /* Filter bit 26 */
6776 #define CAN_F3R2_FB27 ((u32)0x08000000) /* Filter bit 27 */
6777 #define CAN_F3R2_FB28 ((u32)0x10000000) /* Filter bit 28 */
6778 #define CAN_F3R2_FB29 ((u32)0x20000000) /* Filter bit 29 */
6779 #define CAN_F3R2_FB30 ((u32)0x40000000) /* Filter bit 30 */
6780 #define CAN_F3R2_FB31 ((u32)0x80000000) /* Filter bit 31 */
6781 
6782 
6783 /******************* Bit definition for CAN_F4R2 register *******************/
6784 #define CAN_F4R2_FB0 ((u32)0x00000001) /* Filter bit 0 */
6785 #define CAN_F4R2_FB1 ((u32)0x00000002) /* Filter bit 1 */
6786 #define CAN_F4R2_FB2 ((u32)0x00000004) /* Filter bit 2 */
6787 #define CAN_F4R2_FB3 ((u32)0x00000008) /* Filter bit 3 */
6788 #define CAN_F4R2_FB4 ((u32)0x00000010) /* Filter bit 4 */
6789 #define CAN_F4R2_FB5 ((u32)0x00000020) /* Filter bit 5 */
6790 #define CAN_F4R2_FB6 ((u32)0x00000040) /* Filter bit 6 */
6791 #define CAN_F4R2_FB7 ((u32)0x00000080) /* Filter bit 7 */
6792 #define CAN_F4R2_FB8 ((u32)0x00000100) /* Filter bit 8 */
6793 #define CAN_F4R2_FB9 ((u32)0x00000200) /* Filter bit 9 */
6794 #define CAN_F4R2_FB10 ((u32)0x00000400) /* Filter bit 10 */
6795 #define CAN_F4R2_FB11 ((u32)0x00000800) /* Filter bit 11 */
6796 #define CAN_F4R2_FB12 ((u32)0x00001000) /* Filter bit 12 */
6797 #define CAN_F4R2_FB13 ((u32)0x00002000) /* Filter bit 13 */
6798 #define CAN_F4R2_FB14 ((u32)0x00004000) /* Filter bit 14 */
6799 #define CAN_F4R2_FB15 ((u32)0x00008000) /* Filter bit 15 */
6800 #define CAN_F4R2_FB16 ((u32)0x00010000) /* Filter bit 16 */
6801 #define CAN_F4R2_FB17 ((u32)0x00020000) /* Filter bit 17 */
6802 #define CAN_F4R2_FB18 ((u32)0x00040000) /* Filter bit 18 */
6803 #define CAN_F4R2_FB19 ((u32)0x00080000) /* Filter bit 19 */
6804 #define CAN_F4R2_FB20 ((u32)0x00100000) /* Filter bit 20 */
6805 #define CAN_F4R2_FB21 ((u32)0x00200000) /* Filter bit 21 */
6806 #define CAN_F4R2_FB22 ((u32)0x00400000) /* Filter bit 22 */
6807 #define CAN_F4R2_FB23 ((u32)0x00800000) /* Filter bit 23 */
6808 #define CAN_F4R2_FB24 ((u32)0x01000000) /* Filter bit 24 */
6809 #define CAN_F4R2_FB25 ((u32)0x02000000) /* Filter bit 25 */
6810 #define CAN_F4R2_FB26 ((u32)0x04000000) /* Filter bit 26 */
6811 #define CAN_F4R2_FB27 ((u32)0x08000000) /* Filter bit 27 */
6812 #define CAN_F4R2_FB28 ((u32)0x10000000) /* Filter bit 28 */
6813 #define CAN_F4R2_FB29 ((u32)0x20000000) /* Filter bit 29 */
6814 #define CAN_F4R2_FB30 ((u32)0x40000000) /* Filter bit 30 */
6815 #define CAN_F4R2_FB31 ((u32)0x80000000) /* Filter bit 31 */
6816 
6817 
6818 /******************* Bit definition for CAN_F5R2 register *******************/
6819 #define CAN_F5R2_FB0 ((u32)0x00000001) /* Filter bit 0 */
6820 #define CAN_F5R2_FB1 ((u32)0x00000002) /* Filter bit 1 */
6821 #define CAN_F5R2_FB2 ((u32)0x00000004) /* Filter bit 2 */
6822 #define CAN_F5R2_FB3 ((u32)0x00000008) /* Filter bit 3 */
6823 #define CAN_F5R2_FB4 ((u32)0x00000010) /* Filter bit 4 */
6824 #define CAN_F5R2_FB5 ((u32)0x00000020) /* Filter bit 5 */
6825 #define CAN_F5R2_FB6 ((u32)0x00000040) /* Filter bit 6 */
6826 #define CAN_F5R2_FB7 ((u32)0x00000080) /* Filter bit 7 */
6827 #define CAN_F5R2_FB8 ((u32)0x00000100) /* Filter bit 8 */
6828 #define CAN_F5R2_FB9 ((u32)0x00000200) /* Filter bit 9 */
6829 #define CAN_F5R2_FB10 ((u32)0x00000400) /* Filter bit 10 */
6830 #define CAN_F5R2_FB11 ((u32)0x00000800) /* Filter bit 11 */
6831 #define CAN_F5R2_FB12 ((u32)0x00001000) /* Filter bit 12 */
6832 #define CAN_F5R2_FB13 ((u32)0x00002000) /* Filter bit 13 */
6833 #define CAN_F5R2_FB14 ((u32)0x00004000) /* Filter bit 14 */
6834 #define CAN_F5R2_FB15 ((u32)0x00008000) /* Filter bit 15 */
6835 #define CAN_F5R2_FB16 ((u32)0x00010000) /* Filter bit 16 */
6836 #define CAN_F5R2_FB17 ((u32)0x00020000) /* Filter bit 17 */
6837 #define CAN_F5R2_FB18 ((u32)0x00040000) /* Filter bit 18 */
6838 #define CAN_F5R2_FB19 ((u32)0x00080000) /* Filter bit 19 */
6839 #define CAN_F5R2_FB20 ((u32)0x00100000) /* Filter bit 20 */
6840 #define CAN_F5R2_FB21 ((u32)0x00200000) /* Filter bit 21 */
6841 #define CAN_F5R2_FB22 ((u32)0x00400000) /* Filter bit 22 */
6842 #define CAN_F5R2_FB23 ((u32)0x00800000) /* Filter bit 23 */
6843 #define CAN_F5R2_FB24 ((u32)0x01000000) /* Filter bit 24 */
6844 #define CAN_F5R2_FB25 ((u32)0x02000000) /* Filter bit 25 */
6845 #define CAN_F5R2_FB26 ((u32)0x04000000) /* Filter bit 26 */
6846 #define CAN_F5R2_FB27 ((u32)0x08000000) /* Filter bit 27 */
6847 #define CAN_F5R2_FB28 ((u32)0x10000000) /* Filter bit 28 */
6848 #define CAN_F5R2_FB29 ((u32)0x20000000) /* Filter bit 29 */
6849 #define CAN_F5R2_FB30 ((u32)0x40000000) /* Filter bit 30 */
6850 #define CAN_F5R2_FB31 ((u32)0x80000000) /* Filter bit 31 */
6851 
6852 
6853 /******************* Bit definition for CAN_F6R2 register *******************/
6854 #define CAN_F6R2_FB0 ((u32)0x00000001) /* Filter bit 0 */
6855 #define CAN_F6R2_FB1 ((u32)0x00000002) /* Filter bit 1 */
6856 #define CAN_F6R2_FB2 ((u32)0x00000004) /* Filter bit 2 */
6857 #define CAN_F6R2_FB3 ((u32)0x00000008) /* Filter bit 3 */
6858 #define CAN_F6R2_FB4 ((u32)0x00000010) /* Filter bit 4 */
6859 #define CAN_F6R2_FB5 ((u32)0x00000020) /* Filter bit 5 */
6860 #define CAN_F6R2_FB6 ((u32)0x00000040) /* Filter bit 6 */
6861 #define CAN_F6R2_FB7 ((u32)0x00000080) /* Filter bit 7 */
6862 #define CAN_F6R2_FB8 ((u32)0x00000100) /* Filter bit 8 */
6863 #define CAN_F6R2_FB9 ((u32)0x00000200) /* Filter bit 9 */
6864 #define CAN_F6R2_FB10 ((u32)0x00000400) /* Filter bit 10 */
6865 #define CAN_F6R2_FB11 ((u32)0x00000800) /* Filter bit 11 */
6866 #define CAN_F6R2_FB12 ((u32)0x00001000) /* Filter bit 12 */
6867 #define CAN_F6R2_FB13 ((u32)0x00002000) /* Filter bit 13 */
6868 #define CAN_F6R2_FB14 ((u32)0x00004000) /* Filter bit 14 */
6869 #define CAN_F6R2_FB15 ((u32)0x00008000) /* Filter bit 15 */
6870 #define CAN_F6R2_FB16 ((u32)0x00010000) /* Filter bit 16 */
6871 #define CAN_F6R2_FB17 ((u32)0x00020000) /* Filter bit 17 */
6872 #define CAN_F6R2_FB18 ((u32)0x00040000) /* Filter bit 18 */
6873 #define CAN_F6R2_FB19 ((u32)0x00080000) /* Filter bit 19 */
6874 #define CAN_F6R2_FB20 ((u32)0x00100000) /* Filter bit 20 */
6875 #define CAN_F6R2_FB21 ((u32)0x00200000) /* Filter bit 21 */
6876 #define CAN_F6R2_FB22 ((u32)0x00400000) /* Filter bit 22 */
6877 #define CAN_F6R2_FB23 ((u32)0x00800000) /* Filter bit 23 */
6878 #define CAN_F6R2_FB24 ((u32)0x01000000) /* Filter bit 24 */
6879 #define CAN_F6R2_FB25 ((u32)0x02000000) /* Filter bit 25 */
6880 #define CAN_F6R2_FB26 ((u32)0x04000000) /* Filter bit 26 */
6881 #define CAN_F6R2_FB27 ((u32)0x08000000) /* Filter bit 27 */
6882 #define CAN_F6R2_FB28 ((u32)0x10000000) /* Filter bit 28 */
6883 #define CAN_F6R2_FB29 ((u32)0x20000000) /* Filter bit 29 */
6884 #define CAN_F6R2_FB30 ((u32)0x40000000) /* Filter bit 30 */
6885 #define CAN_F6R2_FB31 ((u32)0x80000000) /* Filter bit 31 */
6886 
6887 
6888 /******************* Bit definition for CAN_F7R2 register *******************/
6889 #define CAN_F7R2_FB0 ((u32)0x00000001) /* Filter bit 0 */
6890 #define CAN_F7R2_FB1 ((u32)0x00000002) /* Filter bit 1 */
6891 #define CAN_F7R2_FB2 ((u32)0x00000004) /* Filter bit 2 */
6892 #define CAN_F7R2_FB3 ((u32)0x00000008) /* Filter bit 3 */
6893 #define CAN_F7R2_FB4 ((u32)0x00000010) /* Filter bit 4 */
6894 #define CAN_F7R2_FB5 ((u32)0x00000020) /* Filter bit 5 */
6895 #define CAN_F7R2_FB6 ((u32)0x00000040) /* Filter bit 6 */
6896 #define CAN_F7R2_FB7 ((u32)0x00000080) /* Filter bit 7 */
6897 #define CAN_F7R2_FB8 ((u32)0x00000100) /* Filter bit 8 */
6898 #define CAN_F7R2_FB9 ((u32)0x00000200) /* Filter bit 9 */
6899 #define CAN_F7R2_FB10 ((u32)0x00000400) /* Filter bit 10 */
6900 #define CAN_F7R2_FB11 ((u32)0x00000800) /* Filter bit 11 */
6901 #define CAN_F7R2_FB12 ((u32)0x00001000) /* Filter bit 12 */
6902 #define CAN_F7R2_FB13 ((u32)0x00002000) /* Filter bit 13 */
6903 #define CAN_F7R2_FB14 ((u32)0x00004000) /* Filter bit 14 */
6904 #define CAN_F7R2_FB15 ((u32)0x00008000) /* Filter bit 15 */
6905 #define CAN_F7R2_FB16 ((u32)0x00010000) /* Filter bit 16 */
6906 #define CAN_F7R2_FB17 ((u32)0x00020000) /* Filter bit 17 */
6907 #define CAN_F7R2_FB18 ((u32)0x00040000) /* Filter bit 18 */
6908 #define CAN_F7R2_FB19 ((u32)0x00080000) /* Filter bit 19 */
6909 #define CAN_F7R2_FB20 ((u32)0x00100000) /* Filter bit 20 */
6910 #define CAN_F7R2_FB21 ((u32)0x00200000) /* Filter bit 21 */
6911 #define CAN_F7R2_FB22 ((u32)0x00400000) /* Filter bit 22 */
6912 #define CAN_F7R2_FB23 ((u32)0x00800000) /* Filter bit 23 */
6913 #define CAN_F7R2_FB24 ((u32)0x01000000) /* Filter bit 24 */
6914 #define CAN_F7R2_FB25 ((u32)0x02000000) /* Filter bit 25 */
6915 #define CAN_F7R2_FB26 ((u32)0x04000000) /* Filter bit 26 */
6916 #define CAN_F7R2_FB27 ((u32)0x08000000) /* Filter bit 27 */
6917 #define CAN_F7R2_FB28 ((u32)0x10000000) /* Filter bit 28 */
6918 #define CAN_F7R2_FB29 ((u32)0x20000000) /* Filter bit 29 */
6919 #define CAN_F7R2_FB30 ((u32)0x40000000) /* Filter bit 30 */
6920 #define CAN_F7R2_FB31 ((u32)0x80000000) /* Filter bit 31 */
6921 
6922 
6923 /******************* Bit definition for CAN_F8R2 register *******************/
6924 #define CAN_F8R2_FB0 ((u32)0x00000001) /* Filter bit 0 */
6925 #define CAN_F8R2_FB1 ((u32)0x00000002) /* Filter bit 1 */
6926 #define CAN_F8R2_FB2 ((u32)0x00000004) /* Filter bit 2 */
6927 #define CAN_F8R2_FB3 ((u32)0x00000008) /* Filter bit 3 */
6928 #define CAN_F8R2_FB4 ((u32)0x00000010) /* Filter bit 4 */
6929 #define CAN_F8R2_FB5 ((u32)0x00000020) /* Filter bit 5 */
6930 #define CAN_F8R2_FB6 ((u32)0x00000040) /* Filter bit 6 */
6931 #define CAN_F8R2_FB7 ((u32)0x00000080) /* Filter bit 7 */
6932 #define CAN_F8R2_FB8 ((u32)0x00000100) /* Filter bit 8 */
6933 #define CAN_F8R2_FB9 ((u32)0x00000200) /* Filter bit 9 */
6934 #define CAN_F8R2_FB10 ((u32)0x00000400) /* Filter bit 10 */
6935 #define CAN_F8R2_FB11 ((u32)0x00000800) /* Filter bit 11 */
6936 #define CAN_F8R2_FB12 ((u32)0x00001000) /* Filter bit 12 */
6937 #define CAN_F8R2_FB13 ((u32)0x00002000) /* Filter bit 13 */
6938 #define CAN_F8R2_FB14 ((u32)0x00004000) /* Filter bit 14 */
6939 #define CAN_F8R2_FB15 ((u32)0x00008000) /* Filter bit 15 */
6940 #define CAN_F8R2_FB16 ((u32)0x00010000) /* Filter bit 16 */
6941 #define CAN_F8R2_FB17 ((u32)0x00020000) /* Filter bit 17 */
6942 #define CAN_F8R2_FB18 ((u32)0x00040000) /* Filter bit 18 */
6943 #define CAN_F8R2_FB19 ((u32)0x00080000) /* Filter bit 19 */
6944 #define CAN_F8R2_FB20 ((u32)0x00100000) /* Filter bit 20 */
6945 #define CAN_F8R2_FB21 ((u32)0x00200000) /* Filter bit 21 */
6946 #define CAN_F8R2_FB22 ((u32)0x00400000) /* Filter bit 22 */
6947 #define CAN_F8R2_FB23 ((u32)0x00800000) /* Filter bit 23 */
6948 #define CAN_F8R2_FB24 ((u32)0x01000000) /* Filter bit 24 */
6949 #define CAN_F8R2_FB25 ((u32)0x02000000) /* Filter bit 25 */
6950 #define CAN_F8R2_FB26 ((u32)0x04000000) /* Filter bit 26 */
6951 #define CAN_F8R2_FB27 ((u32)0x08000000) /* Filter bit 27 */
6952 #define CAN_F8R2_FB28 ((u32)0x10000000) /* Filter bit 28 */
6953 #define CAN_F8R2_FB29 ((u32)0x20000000) /* Filter bit 29 */
6954 #define CAN_F8R2_FB30 ((u32)0x40000000) /* Filter bit 30 */
6955 #define CAN_F8R2_FB31 ((u32)0x80000000) /* Filter bit 31 */
6956 
6957 
6958 /******************* Bit definition for CAN_F9R2 register *******************/
6959 #define CAN_F9R2_FB0 ((u32)0x00000001) /* Filter bit 0 */
6960 #define CAN_F9R2_FB1 ((u32)0x00000002) /* Filter bit 1 */
6961 #define CAN_F9R2_FB2 ((u32)0x00000004) /* Filter bit 2 */
6962 #define CAN_F9R2_FB3 ((u32)0x00000008) /* Filter bit 3 */
6963 #define CAN_F9R2_FB4 ((u32)0x00000010) /* Filter bit 4 */
6964 #define CAN_F9R2_FB5 ((u32)0x00000020) /* Filter bit 5 */
6965 #define CAN_F9R2_FB6 ((u32)0x00000040) /* Filter bit 6 */
6966 #define CAN_F9R2_FB7 ((u32)0x00000080) /* Filter bit 7 */
6967 #define CAN_F9R2_FB8 ((u32)0x00000100) /* Filter bit 8 */
6968 #define CAN_F9R2_FB9 ((u32)0x00000200) /* Filter bit 9 */
6969 #define CAN_F9R2_FB10 ((u32)0x00000400) /* Filter bit 10 */
6970 #define CAN_F9R2_FB11 ((u32)0x00000800) /* Filter bit 11 */
6971 #define CAN_F9R2_FB12 ((u32)0x00001000) /* Filter bit 12 */
6972 #define CAN_F9R2_FB13 ((u32)0x00002000) /* Filter bit 13 */
6973 #define CAN_F9R2_FB14 ((u32)0x00004000) /* Filter bit 14 */
6974 #define CAN_F9R2_FB15 ((u32)0x00008000) /* Filter bit 15 */
6975 #define CAN_F9R2_FB16 ((u32)0x00010000) /* Filter bit 16 */
6976 #define CAN_F9R2_FB17 ((u32)0x00020000) /* Filter bit 17 */
6977 #define CAN_F9R2_FB18 ((u32)0x00040000) /* Filter bit 18 */
6978 #define CAN_F9R2_FB19 ((u32)0x00080000) /* Filter bit 19 */
6979 #define CAN_F9R2_FB20 ((u32)0x00100000) /* Filter bit 20 */
6980 #define CAN_F9R2_FB21 ((u32)0x00200000) /* Filter bit 21 */
6981 #define CAN_F9R2_FB22 ((u32)0x00400000) /* Filter bit 22 */
6982 #define CAN_F9R2_FB23 ((u32)0x00800000) /* Filter bit 23 */
6983 #define CAN_F9R2_FB24 ((u32)0x01000000) /* Filter bit 24 */
6984 #define CAN_F9R2_FB25 ((u32)0x02000000) /* Filter bit 25 */
6985 #define CAN_F9R2_FB26 ((u32)0x04000000) /* Filter bit 26 */
6986 #define CAN_F9R2_FB27 ((u32)0x08000000) /* Filter bit 27 */
6987 #define CAN_F9R2_FB28 ((u32)0x10000000) /* Filter bit 28 */
6988 #define CAN_F9R2_FB29 ((u32)0x20000000) /* Filter bit 29 */
6989 #define CAN_F9R2_FB30 ((u32)0x40000000) /* Filter bit 30 */
6990 #define CAN_F9R2_FB31 ((u32)0x80000000) /* Filter bit 31 */
6991 
6992 
6993 /******************* Bit definition for CAN_F10R2 register ******************/
6994 #define CAN_F10R2_FB0 ((u32)0x00000001) /* Filter bit 0 */
6995 #define CAN_F10R2_FB1 ((u32)0x00000002) /* Filter bit 1 */
6996 #define CAN_F10R2_FB2 ((u32)0x00000004) /* Filter bit 2 */
6997 #define CAN_F10R2_FB3 ((u32)0x00000008) /* Filter bit 3 */
6998 #define CAN_F10R2_FB4 ((u32)0x00000010) /* Filter bit 4 */
6999 #define CAN_F10R2_FB5 ((u32)0x00000020) /* Filter bit 5 */
7000 #define CAN_F10R2_FB6 ((u32)0x00000040) /* Filter bit 6 */
7001 #define CAN_F10R2_FB7 ((u32)0x00000080) /* Filter bit 7 */
7002 #define CAN_F10R2_FB8 ((u32)0x00000100) /* Filter bit 8 */
7003 #define CAN_F10R2_FB9 ((u32)0x00000200) /* Filter bit 9 */
7004 #define CAN_F10R2_FB10 ((u32)0x00000400) /* Filter bit 10 */
7005 #define CAN_F10R2_FB11 ((u32)0x00000800) /* Filter bit 11 */
7006 #define CAN_F10R2_FB12 ((u32)0x00001000) /* Filter bit 12 */
7007 #define CAN_F10R2_FB13 ((u32)0x00002000) /* Filter bit 13 */
7008 #define CAN_F10R2_FB14 ((u32)0x00004000) /* Filter bit 14 */
7009 #define CAN_F10R2_FB15 ((u32)0x00008000) /* Filter bit 15 */
7010 #define CAN_F10R2_FB16 ((u32)0x00010000) /* Filter bit 16 */
7011 #define CAN_F10R2_FB17 ((u32)0x00020000) /* Filter bit 17 */
7012 #define CAN_F10R2_FB18 ((u32)0x00040000) /* Filter bit 18 */
7013 #define CAN_F10R2_FB19 ((u32)0x00080000) /* Filter bit 19 */
7014 #define CAN_F10R2_FB20 ((u32)0x00100000) /* Filter bit 20 */
7015 #define CAN_F10R2_FB21 ((u32)0x00200000) /* Filter bit 21 */
7016 #define CAN_F10R2_FB22 ((u32)0x00400000) /* Filter bit 22 */
7017 #define CAN_F10R2_FB23 ((u32)0x00800000) /* Filter bit 23 */
7018 #define CAN_F10R2_FB24 ((u32)0x01000000) /* Filter bit 24 */
7019 #define CAN_F10R2_FB25 ((u32)0x02000000) /* Filter bit 25 */
7020 #define CAN_F10R2_FB26 ((u32)0x04000000) /* Filter bit 26 */
7021 #define CAN_F10R2_FB27 ((u32)0x08000000) /* Filter bit 27 */
7022 #define CAN_F10R2_FB28 ((u32)0x10000000) /* Filter bit 28 */
7023 #define CAN_F10R2_FB29 ((u32)0x20000000) /* Filter bit 29 */
7024 #define CAN_F10R2_FB30 ((u32)0x40000000) /* Filter bit 30 */
7025 #define CAN_F10R2_FB31 ((u32)0x80000000) /* Filter bit 31 */
7026 
7027 
7028 /******************* Bit definition for CAN_F11R2 register ******************/
7029 #define CAN_F11R2_FB0 ((u32)0x00000001) /* Filter bit 0 */
7030 #define CAN_F11R2_FB1 ((u32)0x00000002) /* Filter bit 1 */
7031 #define CAN_F11R2_FB2 ((u32)0x00000004) /* Filter bit 2 */
7032 #define CAN_F11R2_FB3 ((u32)0x00000008) /* Filter bit 3 */
7033 #define CAN_F11R2_FB4 ((u32)0x00000010) /* Filter bit 4 */
7034 #define CAN_F11R2_FB5 ((u32)0x00000020) /* Filter bit 5 */
7035 #define CAN_F11R2_FB6 ((u32)0x00000040) /* Filter bit 6 */
7036 #define CAN_F11R2_FB7 ((u32)0x00000080) /* Filter bit 7 */
7037 #define CAN_F11R2_FB8 ((u32)0x00000100) /* Filter bit 8 */
7038 #define CAN_F11R2_FB9 ((u32)0x00000200) /* Filter bit 9 */
7039 #define CAN_F11R2_FB10 ((u32)0x00000400) /* Filter bit 10 */
7040 #define CAN_F11R2_FB11 ((u32)0x00000800) /* Filter bit 11 */
7041 #define CAN_F11R2_FB12 ((u32)0x00001000) /* Filter bit 12 */
7042 #define CAN_F11R2_FB13 ((u32)0x00002000) /* Filter bit 13 */
7043 #define CAN_F11R2_FB14 ((u32)0x00004000) /* Filter bit 14 */
7044 #define CAN_F11R2_FB15 ((u32)0x00008000) /* Filter bit 15 */
7045 #define CAN_F11R2_FB16 ((u32)0x00010000) /* Filter bit 16 */
7046 #define CAN_F11R2_FB17 ((u32)0x00020000) /* Filter bit 17 */
7047 #define CAN_F11R2_FB18 ((u32)0x00040000) /* Filter bit 18 */
7048 #define CAN_F11R2_FB19 ((u32)0x00080000) /* Filter bit 19 */
7049 #define CAN_F11R2_FB20 ((u32)0x00100000) /* Filter bit 20 */
7050 #define CAN_F11R2_FB21 ((u32)0x00200000) /* Filter bit 21 */
7051 #define CAN_F11R2_FB22 ((u32)0x00400000) /* Filter bit 22 */
7052 #define CAN_F11R2_FB23 ((u32)0x00800000) /* Filter bit 23 */
7053 #define CAN_F11R2_FB24 ((u32)0x01000000) /* Filter bit 24 */
7054 #define CAN_F11R2_FB25 ((u32)0x02000000) /* Filter bit 25 */
7055 #define CAN_F11R2_FB26 ((u32)0x04000000) /* Filter bit 26 */
7056 #define CAN_F11R2_FB27 ((u32)0x08000000) /* Filter bit 27 */
7057 #define CAN_F11R2_FB28 ((u32)0x10000000) /* Filter bit 28 */
7058 #define CAN_F11R2_FB29 ((u32)0x20000000) /* Filter bit 29 */
7059 #define CAN_F11R2_FB30 ((u32)0x40000000) /* Filter bit 30 */
7060 #define CAN_F11R2_FB31 ((u32)0x80000000) /* Filter bit 31 */
7061 
7062 
7063 /******************* Bit definition for CAN_F12R2 register ******************/
7064 #define CAN_F12R2_FB0 ((u32)0x00000001) /* Filter bit 0 */
7065 #define CAN_F12R2_FB1 ((u32)0x00000002) /* Filter bit 1 */
7066 #define CAN_F12R2_FB2 ((u32)0x00000004) /* Filter bit 2 */
7067 #define CAN_F12R2_FB3 ((u32)0x00000008) /* Filter bit 3 */
7068 #define CAN_F12R2_FB4 ((u32)0x00000010) /* Filter bit 4 */
7069 #define CAN_F12R2_FB5 ((u32)0x00000020) /* Filter bit 5 */
7070 #define CAN_F12R2_FB6 ((u32)0x00000040) /* Filter bit 6 */
7071 #define CAN_F12R2_FB7 ((u32)0x00000080) /* Filter bit 7 */
7072 #define CAN_F12R2_FB8 ((u32)0x00000100) /* Filter bit 8 */
7073 #define CAN_F12R2_FB9 ((u32)0x00000200) /* Filter bit 9 */
7074 #define CAN_F12R2_FB10 ((u32)0x00000400) /* Filter bit 10 */
7075 #define CAN_F12R2_FB11 ((u32)0x00000800) /* Filter bit 11 */
7076 #define CAN_F12R2_FB12 ((u32)0x00001000) /* Filter bit 12 */
7077 #define CAN_F12R2_FB13 ((u32)0x00002000) /* Filter bit 13 */
7078 #define CAN_F12R2_FB14 ((u32)0x00004000) /* Filter bit 14 */
7079 #define CAN_F12R2_FB15 ((u32)0x00008000) /* Filter bit 15 */
7080 #define CAN_F12R2_FB16 ((u32)0x00010000) /* Filter bit 16 */
7081 #define CAN_F12R2_FB17 ((u32)0x00020000) /* Filter bit 17 */
7082 #define CAN_F12R2_FB18 ((u32)0x00040000) /* Filter bit 18 */
7083 #define CAN_F12R2_FB19 ((u32)0x00080000) /* Filter bit 19 */
7084 #define CAN_F12R2_FB20 ((u32)0x00100000) /* Filter bit 20 */
7085 #define CAN_F12R2_FB21 ((u32)0x00200000) /* Filter bit 21 */
7086 #define CAN_F12R2_FB22 ((u32)0x00400000) /* Filter bit 22 */
7087 #define CAN_F12R2_FB23 ((u32)0x00800000) /* Filter bit 23 */
7088 #define CAN_F12R2_FB24 ((u32)0x01000000) /* Filter bit 24 */
7089 #define CAN_F12R2_FB25 ((u32)0x02000000) /* Filter bit 25 */
7090 #define CAN_F12R2_FB26 ((u32)0x04000000) /* Filter bit 26 */
7091 #define CAN_F12R2_FB27 ((u32)0x08000000) /* Filter bit 27 */
7092 #define CAN_F12R2_FB28 ((u32)0x10000000) /* Filter bit 28 */
7093 #define CAN_F12R2_FB29 ((u32)0x20000000) /* Filter bit 29 */
7094 #define CAN_F12R2_FB30 ((u32)0x40000000) /* Filter bit 30 */
7095 #define CAN_F12R2_FB31 ((u32)0x80000000) /* Filter bit 31 */
7096 
7097 
7098 /******************* Bit definition for CAN_F13R2 register ******************/
7099 #define CAN_F13R2_FB0 ((u32)0x00000001) /* Filter bit 0 */
7100 #define CAN_F13R2_FB1 ((u32)0x00000002) /* Filter bit 1 */
7101 #define CAN_F13R2_FB2 ((u32)0x00000004) /* Filter bit 2 */
7102 #define CAN_F13R2_FB3 ((u32)0x00000008) /* Filter bit 3 */
7103 #define CAN_F13R2_FB4 ((u32)0x00000010) /* Filter bit 4 */
7104 #define CAN_F13R2_FB5 ((u32)0x00000020) /* Filter bit 5 */
7105 #define CAN_F13R2_FB6 ((u32)0x00000040) /* Filter bit 6 */
7106 #define CAN_F13R2_FB7 ((u32)0x00000080) /* Filter bit 7 */
7107 #define CAN_F13R2_FB8 ((u32)0x00000100) /* Filter bit 8 */
7108 #define CAN_F13R2_FB9 ((u32)0x00000200) /* Filter bit 9 */
7109 #define CAN_F13R2_FB10 ((u32)0x00000400) /* Filter bit 10 */
7110 #define CAN_F13R2_FB11 ((u32)0x00000800) /* Filter bit 11 */
7111 #define CAN_F13R2_FB12 ((u32)0x00001000) /* Filter bit 12 */
7112 #define CAN_F13R2_FB13 ((u32)0x00002000) /* Filter bit 13 */
7113 #define CAN_F13R2_FB14 ((u32)0x00004000) /* Filter bit 14 */
7114 #define CAN_F13R2_FB15 ((u32)0x00008000) /* Filter bit 15 */
7115 #define CAN_F13R2_FB16 ((u32)0x00010000) /* Filter bit 16 */
7116 #define CAN_F13R2_FB17 ((u32)0x00020000) /* Filter bit 17 */
7117 #define CAN_F13R2_FB18 ((u32)0x00040000) /* Filter bit 18 */
7118 #define CAN_F13R2_FB19 ((u32)0x00080000) /* Filter bit 19 */
7119 #define CAN_F13R2_FB20 ((u32)0x00100000) /* Filter bit 20 */
7120 #define CAN_F13R2_FB21 ((u32)0x00200000) /* Filter bit 21 */
7121 #define CAN_F13R2_FB22 ((u32)0x00400000) /* Filter bit 22 */
7122 #define CAN_F13R2_FB23 ((u32)0x00800000) /* Filter bit 23 */
7123 #define CAN_F13R2_FB24 ((u32)0x01000000) /* Filter bit 24 */
7124 #define CAN_F13R2_FB25 ((u32)0x02000000) /* Filter bit 25 */
7125 #define CAN_F13R2_FB26 ((u32)0x04000000) /* Filter bit 26 */
7126 #define CAN_F13R2_FB27 ((u32)0x08000000) /* Filter bit 27 */
7127 #define CAN_F13R2_FB28 ((u32)0x10000000) /* Filter bit 28 */
7128 #define CAN_F13R2_FB29 ((u32)0x20000000) /* Filter bit 29 */
7129 #define CAN_F13R2_FB30 ((u32)0x40000000) /* Filter bit 30 */
7130 #define CAN_F13R2_FB31 ((u32)0x80000000) /* Filter bit 31 */
7131 
7132 
7133 
7134 /******************************************************************************/
7135 /* */
7136 /* Serial Peripheral Interface */
7137 /* */
7138 /******************************************************************************/
7139 
7140 /******************* Bit definition for SPI_CR1 register ********************/
7141 #define SPI_CR1_CPHA ((u16)0x0001) /* Clock Phase */
7142 #define SPI_CR1_CPOL ((u16)0x0002) /* Clock Polarity */
7143 #define SPI_CR1_MSTR ((u16)0x0004) /* Master Selection */
7144 
7145 #define SPI_CR1_BR ((u16)0x0038) /* BR[2:0] bits (Baud Rate Control) */
7146 #define SPI_CR1_BR_0 ((u16)0x0008) /* Bit 0 */
7147 #define SPI_CR1_BR_1 ((u16)0x0010) /* Bit 1 */
7148 #define SPI_CR1_BR_2 ((u16)0x0020) /* Bit 2 */
7149 
7150 #define SPI_CR1_SPE ((u16)0x0040) /* SPI Enable */
7151 #define SPI_CR1_LSBFIRST ((u16)0x0080) /* Frame Format */
7152 #define SPI_CR1_SSI ((u16)0x0100) /* Internal slave select */
7153 #define SPI_CR1_SSM ((u16)0x0200) /* Software slave management */
7154 #define SPI_CR1_RXONLY ((u16)0x0400) /* Receive only */
7155 #define SPI_CR1_DFF ((u16)0x0800) /* Data Frame Format */
7156 #define SPI_CR1_CRCNEXT ((u16)0x1000) /* Transmit CRC next */
7157 #define SPI_CR1_CRCEN ((u16)0x2000) /* Hardware CRC calculation enable */
7158 #define SPI_CR1_BIDIOE ((u16)0x4000) /* Output enable in bidirectional mode */
7159 #define SPI_CR1_BIDIMODE ((u16)0x8000) /* Bidirectional data mode enable */
7160 
7161 
7162 /******************* Bit definition for SPI_CR2 register ********************/
7163 #define SPI_CR2_RXDMAEN ((u8)0x01) /* Rx Buffer DMA Enable */
7164 #define SPI_CR2_TXDMAEN ((u8)0x02) /* Tx Buffer DMA Enable */
7165 #define SPI_CR2_SSOE ((u8)0x04) /* SS Output Enable */
7166 #define SPI_CR2_ERRIE ((u8)0x20) /* Error Interrupt Enable */
7167 #define SPI_CR2_RXNEIE ((u8)0x40) /* RX buffer Not Empty Interrupt Enable */
7168 #define SPI_CR2_TXEIE ((u8)0x80) /* Tx buffer Empty Interrupt Enable */
7169 
7170 
7171 /******************** Bit definition for SPI_SR register ********************/
7172 #define SPI_SR_RXNE ((u8)0x01) /* Receive buffer Not Empty */
7173 #define SPI_SR_TXE ((u8)0x02) /* Transmit buffer Empty */
7174 #define SPI_SR_CHSIDE ((u8)0x04) /* Channel side */
7175 #define SPI_SR_UDR ((u8)0x08) /* Underrun flag */
7176 #define SPI_SR_CRCERR ((u8)0x10) /* CRC Error flag */
7177 #define SPI_SR_MODF ((u8)0x20) /* Mode fault */
7178 #define SPI_SR_OVR ((u8)0x40) /* Overrun flag */
7179 #define SPI_SR_BSY ((u8)0x80) /* Busy flag */
7180 
7181 
7182 /******************** Bit definition for SPI_DR register ********************/
7183 #define SPI_DR_DR ((u16)0xFFFF) /* Data Register */
7184 
7185 
7186 /******************* Bit definition for SPI_CRCPR register ******************/
7187 #define SPI_CRCPR_CRCPOLY ((u16)0xFFFF) /* CRC polynomial register */
7188 
7189 
7190 /****************** Bit definition for SPI_RXCRCR register ******************/
7191 #define SPI_RXCRCR_RXCRC ((u16)0xFFFF) /* Rx CRC Register */
7192 
7193 
7194 /****************** Bit definition for SPI_TXCRCR register ******************/
7195 #define SPI_TXCRCR_TXCRC ((u16)0xFFFF) /* Tx CRC Register */
7196 
7197 
7198 /****************** Bit definition for SPI_I2SCFGR register *****************/
7199 #define SPI_I2SCFGR_CHLEN ((u16)0x0001) /* Channel length (number of bits per audio channel) */
7200 
7201 #define SPI_I2SCFGR_DATLEN ((u16)0x0006) /* DATLEN[1:0] bits (Data length to be transferred) */
7202 #define SPI_I2SCFGR_DATLEN_0 ((u16)0x0002) /* Bit 0 */
7203 #define SPI_I2SCFGR_DATLEN_1 ((u16)0x0004) /* Bit 1 */
7204 
7205 #define SPI_I2SCFGR_CKPOL ((u16)0x0008) /* steady state clock polarity */
7206 
7207 #define SPI_I2SCFGR_I2SSTD ((u16)0x0030) /* I2SSTD[1:0] bits (I2S standard selection) */
7208 #define SPI_I2SCFGR_I2SSTD_0 ((u16)0x0010) /* Bit 0 */
7209 #define SPI_I2SCFGR_I2SSTD_1 ((u16)0x0020) /* Bit 1 */
7210 
7211 #define SPI_I2SCFGR_PCMSYNC ((u16)0x0080) /* PCM frame synchronization */
7212 
7213 #define SPI_I2SCFGR_I2SCFG ((u16)0x0300) /* I2SCFG[1:0] bits (I2S configuration mode) */
7214 #define SPI_I2SCFGR_I2SCFG_0 ((u16)0x0100) /* Bit 0 */
7215 #define SPI_I2SCFGR_I2SCFG_1 ((u16)0x0200) /* Bit 1 */
7216 
7217 #define SPI_I2SCFGR_I2SE ((u16)0x0400) /* I2S Enable */
7218 #define SPI_I2SCFGR_I2SMOD ((u16)0x0800) /* I2S mode selection */
7219 
7220 
7221 /****************** Bit definition for SPI_I2SPR register *******************/
7222 #define SPI_I2SPR_I2SDIV ((u16)0x00FF) /* I2S Linear prescaler */
7223 #define SPI_I2SPR_ODD ((u16)0x0100) /* Odd factor for the prescaler */
7224 #define SPI_I2SPR_MCKOE ((u16)0x0200) /* Master Clock Output Enable */
7225 
7226 
7227 
7228 /******************************************************************************/
7229 /* */
7230 /* Inter-integrated Circuit Interface */
7231 /* */
7232 /******************************************************************************/
7233 
7234 /******************* Bit definition for I2C_CR1 register ********************/
7235 #define I2C_CR1_PE ((u16)0x0001) /* Peripheral Enable */
7236 #define I2C_CR1_SMBUS ((u16)0x0002) /* SMBus Mode */
7237 #define I2C_CR1_SMBTYPE ((u16)0x0008) /* SMBus Type */
7238 #define I2C_CR1_ENARP ((u16)0x0010) /* ARP Enable */
7239 #define I2C_CR1_ENPEC ((u16)0x0020) /* PEC Enable */
7240 #define I2C_CR1_ENGC ((u16)0x0040) /* General Call Enable */
7241 #define I2C_CR1_NOSTRETCH ((u16)0x0080) /* Clock Stretching Disable (Slave mode) */
7242 #define I2C_CR1_START ((u16)0x0100) /* Start Generation */
7243 #define I2C_CR1_STOP ((u16)0x0200) /* Stop Generation */
7244 #define I2C_CR1_ACK ((u16)0x0400) /* Acknowledge Enable */
7245 #define I2C_CR1_POS ((u16)0x0800) /* Acknowledge/PEC Position (for data reception) */
7246 #define I2C_CR1_PEC ((u16)0x1000) /* Packet Error Checking */
7247 #define I2C_CR1_ALERT ((u16)0x2000) /* SMBus Alert */
7248 #define I2C_CR1_SWRST ((u16)0x8000) /* Software Reset */
7249 
7250 
7251 /******************* Bit definition for I2C_CR2 register ********************/
7252 #define I2C_CR2_FREQ ((u16)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */
7253 #define I2C_CR2_FREQ_0 ((u16)0x0001) /* Bit 0 */
7254 #define I2C_CR2_FREQ_1 ((u16)0x0002) /* Bit 1 */
7255 #define I2C_CR2_FREQ_2 ((u16)0x0004) /* Bit 2 */
7256 #define I2C_CR2_FREQ_3 ((u16)0x0008) /* Bit 3 */
7257 #define I2C_CR2_FREQ_4 ((u16)0x0010) /* Bit 4 */
7258 #define I2C_CR2_FREQ_5 ((u16)0x0020) /* Bit 5 */
7259 
7260 #define I2C_CR2_ITERREN ((u16)0x0100) /* Error Interrupt Enable */
7261 #define I2C_CR2_ITEVTEN ((u16)0x0200) /* Event Interrupt Enable */
7262 #define I2C_CR2_ITBUFEN ((u16)0x0400) /* Buffer Interrupt Enable */
7263 #define I2C_CR2_DMAEN ((u16)0x0800) /* DMA Requests Enable */
7264 #define I2C_CR2_LAST ((u16)0x1000) /* DMA Last Transfer */
7265 
7266 
7267 /******************* Bit definition for I2C_OAR1 register *******************/
7268 #define I2C_OAR1_ADD1_7 ((u16)0x00FE) /* Interface Address */
7269 #define I2C_OAR1_ADD8_9 ((u16)0x0300) /* Interface Address */
7270 
7271 #define I2C_OAR1_ADD0 ((u16)0x0001) /* Bit 0 */
7272 #define I2C_OAR1_ADD1 ((u16)0x0002) /* Bit 1 */
7273 #define I2C_OAR1_ADD2 ((u16)0x0004) /* Bit 2 */
7274 #define I2C_OAR1_ADD3 ((u16)0x0008) /* Bit 3 */
7275 #define I2C_OAR1_ADD4 ((u16)0x0010) /* Bit 4 */
7276 #define I2C_OAR1_ADD5 ((u16)0x0020) /* Bit 5 */
7277 #define I2C_OAR1_ADD6 ((u16)0x0040) /* Bit 6 */
7278 #define I2C_OAR1_ADD7 ((u16)0x0080) /* Bit 7 */
7279 #define I2C_OAR1_ADD8 ((u16)0x0100) /* Bit 8 */
7280 #define I2C_OAR1_ADD9 ((u16)0x0200) /* Bit 9 */
7281 
7282 #define I2C_OAR1_ADDMODE ((u16)0x8000) /* Addressing Mode (Slave mode) */
7283 
7284 
7285 /******************* Bit definition for I2C_OAR2 register *******************/
7286 #define I2C_OAR2_ENDUAL ((u8)0x01) /* Dual addressing mode enable */
7287 #define I2C_OAR2_ADD2 ((u8)0xFE) /* Interface address */
7288 
7289 
7290 /******************** Bit definition for I2C_DR register ********************/
7291 #define I2C_DR_DR ((u8)0xFF) /* 8-bit Data Register */
7292 
7293 
7294 /******************* Bit definition for I2C_SR1 register ********************/
7295 #define I2C_SR1_SB ((u16)0x0001) /* Start Bit (Master mode) */
7296 #define I2C_SR1_ADDR ((u16)0x0002) /* Address sent (master mode)/matched (slave mode) */
7297 #define I2C_SR1_BTF ((u16)0x0004) /* Byte Transfer Finished */
7298 #define I2C_SR1_ADD10 ((u16)0x0008) /* 10-bit header sent (Master mode) */
7299 #define I2C_SR1_STOPF ((u16)0x0010) /* Stop detection (Slave mode) */
7300 #define I2C_SR1_RXNE ((u16)0x0040) /* Data Register not Empty (receivers) */
7301 #define I2C_SR1_TXE ((u16)0x0080) /* Data Register Empty (transmitters) */
7302 #define I2C_SR1_BERR ((u16)0x0100) /* Bus Error */
7303 #define I2C_SR1_ARLO ((u16)0x0200) /* Arbitration Lost (master mode) */
7304 #define I2C_SR1_AF ((u16)0x0400) /* Acknowledge Failure */
7305 #define I2C_SR1_OVR ((u16)0x0800) /* Overrun/Underrun */
7306 #define I2C_SR1_PECERR ((u16)0x1000) /* PEC Error in reception */
7307 #define I2C_SR1_TIMEOUT ((u16)0x4000) /* Timeout or Tlow Error */
7308 #define I2C_SR1_SMBALERT ((u16)0x8000) /* SMBus Alert */
7309 
7310 
7311 /******************* Bit definition for I2C_SR2 register ********************/
7312 #define I2C_SR2_MSL ((u16)0x0001) /* Master/Slave */
7313 #define I2C_SR2_BUSY ((u16)0x0002) /* Bus Busy */
7314 #define I2C_SR2_TRA ((u16)0x0004) /* Transmitter/Receiver */
7315 #define I2C_SR2_GENCALL ((u16)0x0010) /* General Call Address (Slave mode) */
7316 #define I2C_SR2_SMBDEFAULT ((u16)0x0020) /* SMBus Device Default Address (Slave mode) */
7317 #define I2C_SR2_SMBHOST ((u16)0x0040) /* SMBus Host Header (Slave mode) */
7318 #define I2C_SR2_DUALF ((u16)0x0080) /* Dual Flag (Slave mode) */
7319 #define I2C_SR2_PEC ((u16)0xFF00) /* Packet Error Checking Register */
7320 
7321 
7322 /******************* Bit definition for I2C_CCR register ********************/
7323 #define I2C_CCR_CCR ((u16)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */
7324 #define I2C_CCR_DUTY ((u16)0x4000) /* Fast Mode Duty Cycle */
7325 #define I2C_CCR_FS ((u16)0x8000) /* I2C Master Mode Selection */
7326 
7327 
7328 /****************** Bit definition for I2C_TRISE register *******************/
7329 #define I2C_TRISE_TRISE ((u8)0x3F) /* Maximum Rise Time in Fast/Standard mode (Master mode) */
7330 
7331 
7332 
7333 /******************************************************************************/
7334 /* */
7335 /* Universal Synchronous Asynchronous Receiver Transmitter */
7336 /* */
7337 /******************************************************************************/
7338 
7339 /******************* Bit definition for USART_SR register *******************/
7340 #define USART_SR_PE ((u16)0x0001) /* Parity Error */
7341 #define USART_SR_FE ((u16)0x0002) /* Framing Error */
7342 #define USART_SR_NE ((u16)0x0004) /* Noise Error Flag */
7343 #define USART_SR_ORE ((u16)0x0008) /* OverRun Error */
7344 #define USART_SR_IDLE ((u16)0x0010) /* IDLE line detected */
7345 #define USART_SR_RXNE ((u16)0x0020) /* Read Data Register Not Empty */
7346 #define USART_SR_TC ((u16)0x0040) /* Transmission Complete */
7347 #define USART_SR_TXE ((u16)0x0080) /* Transmit Data Register Empty */
7348 #define USART_SR_LBD ((u16)0x0100) /* LIN Break Detection Flag */
7349 #define USART_SR_CTS ((u16)0x0200) /* CTS Flag */
7350 
7351 
7352 /******************* Bit definition for USART_DR register *******************/
7353 #define USART_DR_DR ((u16)0x01FF) /* Data value */
7354 
7355 
7356 /****************** Bit definition for USART_BRR register *******************/
7357 #define USART_BRR_DIV_Fraction ((u16)0x000F) /* Fraction of USARTDIV */
7358 #define USART_BRR_DIV_Mantissa ((u16)0xFFF0) /* Mantissa of USARTDIV */
7359 
7360 
7361 /****************** Bit definition for USART_CR1 register *******************/
7362 #define USART_CR1_SBK ((u16)0x0001) /* Send Break */
7363 #define USART_CR1_RWU ((u16)0x0002) /* Receiver wakeup */
7364 #define USART_CR1_RE ((u16)0x0004) /* Receiver Enable */
7365 #define USART_CR1_TE ((u16)0x0008) /* Transmitter Enable */
7366 #define USART_CR1_IDLEIE ((u16)0x0010) /* IDLE Interrupt Enable */
7367 #define USART_CR1_RXNEIE ((u16)0x0020) /* RXNE Interrupt Enable */
7368 #define USART_CR1_TCIE ((u16)0x0040) /* Transmission Complete Interrupt Enable */
7369 #define USART_CR1_TXEIE ((u16)0x0080) /* PE Interrupt Enable */
7370 #define USART_CR1_PEIE ((u16)0x0100) /* PE Interrupt Enable */
7371 #define USART_CR1_PS ((u16)0x0200) /* Parity Selection */
7372 #define USART_CR1_PCE ((u16)0x0400) /* Parity Control Enable */
7373 #define USART_CR1_WAKE ((u16)0x0800) /* Wakeup method */
7374 #define USART_CR1_M ((u16)0x1000) /* Word length */
7375 #define USART_CR1_UE ((u16)0x2000) /* USART Enable */
7376 
7377 
7378 /****************** Bit definition for USART_CR2 register *******************/
7379 #define USART_CR2_ADD ((u16)0x000F) /* Address of the USART node */
7380 #define USART_CR2_LBDL ((u16)0x0020) /* LIN Break Detection Length */
7381 #define USART_CR2_LBDIE ((u16)0x0040) /* LIN Break Detection Interrupt Enable */
7382 #define USART_CR2_LBCL ((u16)0x0100) /* Last Bit Clock pulse */
7383 #define USART_CR2_CPHA ((u16)0x0200) /* Clock Phase */
7384 #define USART_CR2_CPOL ((u16)0x0400) /* Clock Polarity */
7385 #define USART_CR2_CLKEN ((u16)0x0800) /* Clock Enable */
7386 
7387 #define USART_CR2_STOP ((u16)0x3000) /* STOP[1:0] bits (STOP bits) */
7388 #define USART_CR2_STOP_0 ((u16)0x1000) /* Bit 0 */
7389 #define USART_CR2_STOP_1 ((u16)0x2000) /* Bit 1 */
7390 
7391 #define USART_CR2_LINEN ((u16)0x4000) /* LIN mode enable */
7392 
7393 
7394 /****************** Bit definition for USART_CR3 register *******************/
7395 #define USART_CR3_EIE ((u16)0x0001) /* Error Interrupt Enable */
7396 #define USART_CR3_IREN ((u16)0x0002) /* IrDA mode Enable */
7397 #define USART_CR3_IRLP ((u16)0x0004) /* IrDA Low-Power */
7398 #define USART_CR3_HDSEL ((u16)0x0008) /* Half-Duplex Selection */
7399 #define USART_CR3_NACK ((u16)0x0010) /* Smartcard NACK enable */
7400 #define USART_CR3_SCEN ((u16)0x0020) /* Smartcard mode enable */
7401 #define USART_CR3_DMAR ((u16)0x0040) /* DMA Enable Receiver */
7402 #define USART_CR3_DMAT ((u16)0x0080) /* DMA Enable Transmitter */
7403 #define USART_CR3_RTSE ((u16)0x0100) /* RTS Enable */
7404 #define USART_CR3_CTSE ((u16)0x0200) /* CTS Enable */
7405 #define USART_CR3_CTSIE ((u16)0x0400) /* CTS Interrupt Enable */
7406 
7407 
7408 /****************** Bit definition for USART_GTPR register ******************/
7409 #define USART_GTPR_PSC ((u16)0x00FF) /* PSC[7:0] bits (Prescaler value) */
7410 #define USART_GTPR_PSC_0 ((u16)0x0001) /* Bit 0 */
7411 #define USART_GTPR_PSC_1 ((u16)0x0002) /* Bit 1 */
7412 #define USART_GTPR_PSC_2 ((u16)0x0004) /* Bit 2 */
7413 #define USART_GTPR_PSC_3 ((u16)0x0008) /* Bit 3 */
7414 #define USART_GTPR_PSC_4 ((u16)0x0010) /* Bit 4 */
7415 #define USART_GTPR_PSC_5 ((u16)0x0020) /* Bit 5 */
7416 #define USART_GTPR_PSC_6 ((u16)0x0040) /* Bit 6 */
7417 #define USART_GTPR_PSC_7 ((u16)0x0080) /* Bit 7 */
7418 
7419 #define USART_GTPR_GT ((u16)0xFF00) /* Guard time value */
7420 
7421 
7422 
7423 /******************************************************************************/
7424 /* */
7425 /* Debug MCU */
7426 /* */
7427 /******************************************************************************/
7428 
7429 /**************** Bit definition for DBGMCU_IDCODE register *****************/
7430 #define DBGMCU_IDCODE_DEV_ID ((u32)0x00000FFF) /* Device Identifier */
7431 
7432 #define DBGMCU_IDCODE_REV_ID ((u32)0xFFFF0000) /* REV_ID[15:0] bits (Revision Identifier) */
7433 #define DBGMCU_IDCODE_REV_ID_0 ((u32)0x00010000) /* Bit 0 */
7434 #define DBGMCU_IDCODE_REV_ID_1 ((u32)0x00020000) /* Bit 1 */
7435 #define DBGMCU_IDCODE_REV_ID_2 ((u32)0x00040000) /* Bit 2 */
7436 #define DBGMCU_IDCODE_REV_ID_3 ((u32)0x00080000) /* Bit 3 */
7437 #define DBGMCU_IDCODE_REV_ID_4 ((u32)0x00100000) /* Bit 4 */
7438 #define DBGMCU_IDCODE_REV_ID_5 ((u32)0x00200000) /* Bit 5 */
7439 #define DBGMCU_IDCODE_REV_ID_6 ((u32)0x00400000) /* Bit 6 */
7440 #define DBGMCU_IDCODE_REV_ID_7 ((u32)0x00800000) /* Bit 7 */
7441 #define DBGMCU_IDCODE_REV_ID_8 ((u32)0x01000000) /* Bit 8 */
7442 #define DBGMCU_IDCODE_REV_ID_9 ((u32)0x02000000) /* Bit 9 */
7443 #define DBGMCU_IDCODE_REV_ID_10 ((u32)0x04000000) /* Bit 10 */
7444 #define DBGMCU_IDCODE_REV_ID_11 ((u32)0x08000000) /* Bit 11 */
7445 #define DBGMCU_IDCODE_REV_ID_12 ((u32)0x10000000) /* Bit 12 */
7446 #define DBGMCU_IDCODE_REV_ID_13 ((u32)0x20000000) /* Bit 13 */
7447 #define DBGMCU_IDCODE_REV_ID_14 ((u32)0x40000000) /* Bit 14 */
7448 #define DBGMCU_IDCODE_REV_ID_15 ((u32)0x80000000) /* Bit 15 */
7449 
7450 
7451 /****************** Bit definition for DBGMCU_CR register *******************/
7452 #define DBGMCU_CR_DBG_SLEEP ((u32)0x00000001) /* Debug Sleep Mode */
7453 #define DBGMCU_CR_DBG_STOP ((u32)0x00000002) /* Debug Stop Mode */
7454 #define DBGMCU_CR_DBG_STANDBY ((u32)0x00000004) /* Debug Standby mode */
7455 #define DBGMCU_CR_TRACE_IOEN ((u32)0x00000020) /* Trace Pin Assignment Control */
7456 
7457 #define DBGMCU_CR_TRACE_MODE ((u32)0x000000C0) /* TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
7458 #define DBGMCU_CR_TRACE_MODE_0 ((u32)0x00000040) /* Bit 0 */
7459 #define DBGMCU_CR_TRACE_MODE_1 ((u32)0x00000080) /* Bit 1 */
7460 
7461 #define DBGMCU_CR_DBG_IWDG_STOP ((u32)0x00000100) /* Debug Independent Watchdog stopped when Core is halted */
7462 #define DBGMCU_CR_DBG_WWDG_STOP ((u32)0x00000200) /* Debug Window Watchdog stopped when Core is halted */
7463 #define DBGMCU_CR_DBG_TIM1_STOP ((u32)0x00000400) /* TIM1 counter stopped when core is halted */
7464 #define DBGMCU_CR_DBG_TIM2_STOP ((u32)0x00000800) /* TIM2 counter stopped when core is halted */
7465 #define DBGMCU_CR_DBG_TIM3_STOP ((u32)0x00001000) /* TIM3 counter stopped when core is halted */
7466 #define DBGMCU_CR_DBG_TIM4_STOP ((u32)0x00002000) /* TIM4 counter stopped when core is halted */
7467 #define DBGMCU_CR_DBG_CAN_STOP ((u32)0x00004000) /* Debug CAN stopped when Core is halted */
7468 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((u32)0x00008000) /* SMBUS timeout mode stopped when Core is halted */
7469 #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((u32)0x00010000) /* SMBUS timeout mode stopped when Core is halted */
7470 #define DBGMCU_CR_DBG_TIM5_STOP ((u32)0x00020000) /* TIM5 counter stopped when core is halted */
7471 #define DBGMCU_CR_DBG_TIM6_STOP ((u32)0x00040000) /* TIM6 counter stopped when core is halted */
7472 #define DBGMCU_CR_DBG_TIM7_STOP ((u32)0x00080000) /* TIM7 counter stopped when core is halted */
7473 #define DBGMCU_CR_DBG_TIM8_STOP ((u32)0x00100000) /* TIM8 counter stopped when core is halted */
7474 
7475 
7476 
7477 /******************************************************************************/
7478 /* */
7479 /* FLASH and Option Bytes Registers */
7480 /* */
7481 /******************************************************************************/
7482 
7483 /******************* Bit definition for FLASH_ACR register ******************/
7484 #define FLASH_ACR_LATENCY ((u8)0x07) /* LATENCY[2:0] bits (Latency) */
7485 #define FLASH_ACR_LATENCY_0 ((u8)0x01) /* Bit 0 */
7486 #define FLASH_ACR_LATENCY_1 ((u8)0x02) /* Bit 1 */
7487 #define FLASH_ACR_LATENCY_2 ((u8)0x04) /* Bit 2 */
7488 
7489 #define FLASH_ACR_HLFCYA ((u8)0x08) /* Flash Half Cycle Access Enable */
7490 #define FLASH_ACR_PRFTBE ((u8)0x10) /* Prefetch Buffer Enable */
7491 #define FLASH_ACR_PRFTBS ((u8)0x20) /* Prefetch Buffer Status */
7492 
7493 
7494 /****************** Bit definition for FLASH_KEYR register ******************/
7495 #define FLASH_KEYR_FKEYR ((u32)0xFFFFFFFF) /* FPEC Key */
7496 
7497 
7498 /***************** Bit definition for FLASH_OPTKEYR register ****************/
7499 #define FLASH_OPTKEYR_OPTKEYR ((u32)0xFFFFFFFF) /* Option Byte Key */
7500 
7501 
7502 /****************** Bit definition for FLASH_SR register *******************/
7503 #define FLASH_SR_BSY ((u8)0x01) /* Busy */
7504 #define FLASH_SR_PGERR ((u8)0x04) /* Programming Error */
7505 #define FLASH_SR_WRPRTERR ((u8)0x10) /* Write Protection Error */
7506 #define FLASH_SR_EOP ((u8)0x20) /* End of operation */
7507 
7508 
7509 /******************* Bit definition for FLASH_CR register *******************/
7510 #define FLASH_CR_PG ((u16)0x0001) /* Programming */
7511 #define FLASH_CR_PER ((u16)0x0002) /* Page Erase */
7512 #define FLASH_CR_MER ((u16)0x0004) /* Mass Erase */
7513 #define FLASH_CR_OPTPG ((u16)0x0010) /* Option Byte Programming */
7514 #define FLASH_CR_OPTER ((u16)0x0020) /* Option Byte Erase */
7515 #define FLASH_CR_STRT ((u16)0x0040) /* Start */
7516 #define FLASH_CR_LOCK ((u16)0x0080) /* Lock */
7517 #define FLASH_CR_OPTWRE ((u16)0x0200) /* Option Bytes Write Enable */
7518 #define FLASH_CR_ERRIE ((u16)0x0400) /* Error Interrupt Enable */
7519 #define FLASH_CR_EOPIE ((u16)0x1000) /* End of operation interrupt enable */
7520 
7521 
7522 /******************* Bit definition for FLASH_AR register *******************/
7523 #define FLASH_AR_FAR ((u32)0xFFFFFFFF) /* Flash Address */
7524 
7525 
7526 /****************** Bit definition for FLASH_OBR register *******************/
7527 #define FLASH_OBR_OPTERR ((u16)0x0001) /* Option Byte Error */
7528 #define FLASH_OBR_RDPRT ((u16)0x0002) /* Read protection */
7529 
7530 #define FLASH_OBR_USER ((u16)0x03FC) /* User Option Bytes */
7531 #define FLASH_OBR_WDG_SW ((u16)0x0004) /* WDG_SW */
7532 #define FLASH_OBR_nRST_STOP ((u16)0x0008) /* nRST_STOP */
7533 #define FLASH_OBR_nRST_STDBY ((u16)0x0010) /* nRST_STDBY */
7534 #define FLASH_OBR_Notused ((u16)0x03E0) /* Not used */
7535 
7536 
7537 /****************** Bit definition for FLASH_WRPR register ******************/
7538 #define FLASH_WRPR_WRP ((u32)0xFFFFFFFF) /* Write Protect */
7539 
7540 
7541 /*----------------------------------------------------------------------------*/
7542 
7543 
7544 /****************** Bit definition for FLASH_RDP register *******************/
7545 #define FLASH_RDP_RDP ((u32)0x000000FF) /* Read protection option byte */
7546 #define FLASH_RDP_nRDP ((u32)0x0000FF00) /* Read protection complemented option byte */
7547 
7548 
7549 /****************** Bit definition for FLASH_USER register ******************/
7550 #define FLASH_USER_USER ((u32)0x00FF0000) /* User option byte */
7551 #define FLASH_USER_nUSER ((u32)0xFF000000) /* User complemented option byte */
7552 
7553 
7554 /****************** Bit definition for FLASH_Data0 register *****************/
7555 #define FLASH_Data0_Data0 ((u32)0x000000FF) /* User data storage option byte */
7556 #define FLASH_Data0_nData0 ((u32)0x0000FF00) /* User data storage complemented option byte */
7557 
7558 
7559 /****************** Bit definition for FLASH_Data1 register *****************/
7560 #define FLASH_Data1_Data1 ((u32)0x00FF0000) /* User data storage option byte */
7561 #define FLASH_Data1_nData1 ((u32)0xFF000000) /* User data storage complemented option byte */
7562 
7563 
7564 /****************** Bit definition for FLASH_WRP0 register ******************/
7565 #define FLASH_WRP0_WRP0 ((u32)0x000000FF) /* Flash memory write protection option bytes */
7566 #define FLASH_WRP0_nWRP0 ((u32)0x0000FF00) /* Flash memory write protection complemented option bytes */
7567 
7568 
7569 /****************** Bit definition for FLASH_WRP1 register ******************/
7570 #define FLASH_WRP1_WRP1 ((u32)0x00FF0000) /* Flash memory write protection option bytes */
7571 #define FLASH_WRP1_nWRP1 ((u32)0xFF000000) /* Flash memory write protection complemented option bytes */
7572 
7573 
7574 /****************** Bit definition for FLASH_WRP2 register ******************/
7575 #define FLASH_WRP2_WRP2 ((u32)0x000000FF) /* Flash memory write protection option bytes */
7576 #define FLASH_WRP2_nWRP2 ((u32)0x0000FF00) /* Flash memory write protection complemented option bytes */
7577 
7578 
7579 /****************** Bit definition for FLASH_WRP3 register ******************/
7580 #define FLASH_WRP3_WRP3 ((u32)0x00FF0000) /* Flash memory write protection option bytes */
7581 #define FLASH_WRP3_nWRP3 ((u32)0xFF000000) /* Flash memory write protection complemented option bytes */
7582 
7583 
7584 /* Exported macro ------------------------------------------------------------*/
7585 #define SET_BIT(REG, BIT) ((REG) |= (BIT))
7586 
7587 #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
7588 
7589 #define READ_BIT(REG, BIT) ((REG) & (BIT))
7590 
7591 #define CLEAR_REG(REG) ((REG) = 0x0)
7592 
7593 #define WRITE_REG(REG, VAL) ((REG) = VAL)
7594 
7595 #define READ_REG(REG) ((REG))
7596 
7597 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~CLEARMASK)) | (SETMASK)))
7598 
7599 /* Exported functions ------------------------------------------------------- */
7600 
7601 #endif /* __STM32F10x_MAP_H */
7602 
7603 /******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
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