Contiki 2.5
rtlregs.h
1 #ifndef _DEV_RTLREGS_H_
2 #define _DEV_RTLREGS_H_
3 
4 /*
5  * Copyright (C) 2001-2002 by egnite Software GmbH. All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  *
11  * 1. Redistributions of source code must retain the above copyright
12  * notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  * notice, this list of conditions and the following disclaimer in the
15  * documentation and/or other materials provided with the distribution.
16  * 3. All advertising materials mentioning features or use of this
17  * software must display the following acknowledgement:
18  *
19  * This product includes software developed by egnite Software GmbH
20  * and its contributors.
21  *
22  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
23  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
25  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
26  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
28  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
29  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
30  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
32  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33  * SUCH DAMAGE.
34  *
35  * For additional information see http://www.ethernut.de/
36  *
37  * -
38  * Portions Copyright (C) 2000 David J. Hudson <dave@humbug.demon.co.uk>
39  *
40  * This file is distributed in the hope that it will be useful, but WITHOUT
41  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
42  * FITNESS FOR A PARTICULAR PURPOSE.
43  *
44  * You can redistribute this file and/or modify it under the terms of the GNU
45  * General Public License (GPL) as published by the Free Software Foundation;
46  * either version 2 of the License, or (at your discretion) any later version.
47  * See the accompanying file "copying-gpl.txt" for more details.
48  *
49  * As a special exception to the GPL, permission is granted for additional
50  * uses of the text contained in this file. See the accompanying file
51  * "copying-liquorice.txt" for details.
52  * -
53  * Portions Copyright (c) 1983, 1993 by
54  * The Regents of the University of California. All rights reserved.
55  *
56  * Redistribution and use in source and binary forms, with or without
57  * modification, are permitted provided that the following conditions
58  * are met:
59  * 1. Redistributions of source code must retain the above copyright
60  * notice, this list of conditions and the following disclaimer.
61  * 2. Redistributions in binary form must reproduce the above copyright
62  * notice, this list of conditions and the following disclaimer in the
63  * documentation and/or other materials provided with the distribution.
64  * 3. All advertising materials mentioning features or use of this software
65  * must display the following acknowledgement:
66  * This product includes software developed by the University of
67  * California, Berkeley and its contributors.
68  * 4. Neither the name of the University nor the names of its contributors
69  * may be used to endorse or promote products derived from this software
70  * without specific prior written permission.
71  *
72  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
73  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
74  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
75  * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
76  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
77  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
78  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
79  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
80  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
81  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
82  * SUCH DAMAGE.
83  */
84 
85 /*
86  * $Log: rtlregs.h,v $
87  * Revision 1.1 2006/06/17 22:41:21 adamdunkels
88  * Import of the contiki-2.x development code from the SICS internal CVS server
89  *
90  * Revision 1.1 2005/09/19 23:05:35 adam
91  * AVR device drivers
92  *
93  * Revision 1.1 2005/05/18 19:03:23 adam
94  * Initial import of Contiki AVR port
95  *
96  * Revision 1.1 2003/07/04 10:54:52 adamdunkels
97  * First version of the AVR port
98  *
99  * Revision 1.1 2003/02/05 20:49:07 adam
100  * *** empty log message ***
101  *
102  * Revision 1.6 2002/10/29 15:27:36 harald
103  * *** empty log message ***
104  *
105  * Revision 1.5 2002/06/26 17:29:08 harald
106  * First pre-release with 2.4 stack
107  *
108  */
109 
110 /*!
111  * \brief Realtek 8019AS register definitions.
112  */
113 /*@{*/
114 
115 /*
116  * Register offset applicable to all register pages.
117  */
118 #define NIC_CR 0x00 /*!< \brief Command register */
119 #define NIC_IOPORT 0x10 /*!< \brief I/O data port */
120 #define NIC_RESET 0x1f /*!< \brief Reset port */
121 
122 /*
123  * Page 0 register offsets.
124  */
125 #define NIC_PG0_CLDA0 0x01 /*!< \brief Current local DMA address 0 */
126 #define NIC_PG0_PSTART 0x01 /*!< \brief Page start register */
127 #define NIC_PG0_CLDA1 0x02 /*!< \brief Current local DMA address 1 */
128 #define NIC_PG0_PSTOP 0x02 /*!< \brief Page stop register */
129 #define NIC_PG0_BNRY 0x03 /*!< \brief Boundary pointer */
130 #define NIC_PG0_TSR 0x04 /*!< \brief Transmit status register */
131 #define NIC_PG0_TPSR 0x04 /*!< \brief Transmit page start address */
132 #define NIC_PG0_NCR 0x05 /*!< \brief Number of collisions register */
133 #define NIC_PG0_TBCR0 0x05 /*!< \brief Transmit byte count register 0 */
134 #define NIC_PG0_FIFO 0x06 /*!< \brief FIFO */
135 #define NIC_PG0_TBCR1 0x06 /*!< \brief Transmit byte count register 1 */
136 #define NIC_PG0_ISR 0x07 /*!< \brief Interrupt status register */
137 #define NIC_PG0_CRDA0 0x08 /*!< \brief Current remote DMA address 0 */
138 #define NIC_PG0_RSAR0 0x08 /*!< \brief Remote start address register 0
139  Low byte address to read from the buffer. */
140 #define NIC_PG0_CRDA1 0x09 /*!< \brief Current remote DMA address 1 */
141 #define NIC_PG0_RSAR1 0x09 /*!< \brief Remote start address register 1
142  High byte address to read from the buffer. */
143 #define NIC_PG0_RBCR0 0x0a /*!< \brief Remote byte count register 0
144  Low byte of the number of bytes to read
145  from the buffer. */
146 #define NIC_PG0_RBCR1 0x0b /*!< \brief Remote byte count register 1
147  High byte of the number of bytes to read
148  from the buffer. */
149 #define NIC_PG0_RSR 0x0c /*!< \brief Receive status register */
150 #define NIC_PG0_RCR 0x0c /*!< \brief Receive configuration register */
151 #define NIC_PG0_CNTR0 0x0d /*!< \brief Tally counter 0 (frame alignment errors) */
152 #define NIC_PG0_TCR 0x0d /*!< \brief Transmit configuration register */
153 #define NIC_PG0_CNTR1 0x0e /*!< \brief Tally counter 1 (CRC errors) */
154 #define NIC_PG0_DCR 0x0e /*!< \brief Data configuration register */
155 #define NIC_PG0_CNTR2 0x0f /*!< \brief Tally counter 2 (Missed packet errors) */
156 #define NIC_PG0_IMR 0x0f /*!< \brief Interrupt mask register */
157 
158 /*
159  * Page 1 register offsets.
160  */
161 #define NIC_PG1_PAR0 0x01 /*!< \brief Physical address register 0 */
162 #define NIC_PG1_PAR1 0x02 /*!< \brief Physical address register 1 */
163 #define NIC_PG1_PAR2 0x03 /*!< \brief Physical address register 2 */
164 #define NIC_PG1_PAR3 0x04 /*!< \brief Physical address register 3 */
165 #define NIC_PG1_PAR4 0x05 /*!< \brief Physical address register 4 */
166 #define NIC_PG1_PAR5 0x06 /*!< \brief Physical address register 5 */
167 #define NIC_PG1_CURR 0x07 /*!< \brief Current page register
168  The next incoming packet will be stored
169  at this page address. */
170 #define NIC_PG1_MAR0 0x08 /*!< \brief Multicast address register 0 */
171 #define NIC_PG1_MAR1 0x09 /*!< \brief Multicast address register 1 */
172 #define NIC_PG1_MAR2 0x0a /*!< \brief Multicast address register 2 */
173 #define NIC_PG1_MAR3 0x0b /*!< \brief Multicast address register 3 */
174 #define NIC_PG1_MAR4 0x0c /*!< \brief Multicast address register 4 */
175 #define NIC_PG1_MAR5 0x0d /*!< \brief Multicast address register 5 */
176 #define NIC_PG1_MAR6 0x0e /*!< \brief Multicast address register 6 */
177 #define NIC_PG1_MAR7 0x0f /*!< \brief Multicast address register 7 */
178 
179 /*
180  * Page 2 register offsets.
181  */
182 #define NIC_PG2_PSTART 0x01 /*!< \brief Page start register */
183 #define NIC_PG2_CLDA0 0x01 /*!< \brief Current local DMA address 0 */
184 #define NIC_PG2_PSTOP 0x02 /*!< \brief Page stop register */
185 #define NIC_PG2_CLDA1 0x02 /*!< \brief Current local DMA address 1 */
186 #define NIC_PG2_RNP 0x03 /*!< \brief Remote next packet pointer */
187 #define NIC_PG2_TSPR 0x04 /*!< \brief Transmit page start register */
188 #define NIC_PG2_LNP 0x05 /*!< \brief Local next packet pointer */
189 #define NIC_PG2_ACU 0x06 /*!< \brief Address counter (upper) */
190 #define NIC_PG2_ACL 0x07 /*!< \brief Address counter (lower) */
191 #define NIC_PG2_RCR 0x0c /*!< \brief Receive configuration register */
192 #define NIC_PG2_TCR 0x0d /*!< \brief Transmit configuration register */
193 #define NIC_PG2_DCR 0x0e /*!< \brief Data configuration register */
194 #define NIC_PG2_IMR 0x0f /*!< \brief Interrupt mask register */
195 
196 /*
197  * Page 3 register offsets.
198  */
199 #define NIC_PG3_EECR 0x01 /*!< \brief EEPROM command register */
200 #define NIC_PG3_BPAGE 0x02 /*!< \brief Boot-ROM page register */
201 #define NIC_PG3_CONFIG0 0x03 /*!< \brief Configuration register 0 (r/o) */
202 #define NIC_PG3_CONFIG1 0x04 /*!< \brief Configuration register 1 */
203 #define NIC_PG3_CONFIG2 0x05 /*!< \brief Configuration register 2 */
204 #define NIC_PG3_CONFIG3 0x06 /*!< \brief Configuration register 3 */
205 #define NIC_PG3_CSNSAV 0x08 /*!< \brief CSN save register (r/o) */
206 #define NIC_PG3_HLTCLK 0x09 /*!< \brief Halt clock */
207 #define NIC_PG3_INTR 0x0b /*!< \brief Interrupt pins (r/o) */
208 
209 /*
210  * Command register bits.
211  */
212 #define NIC_CR_STP 0x01 /*!< \brief Stop */
213 #define NIC_CR_STA 0x02 /*!< \brief Start */
214 #define NIC_CR_TXP 0x04 /*!< \brief Transmit packet */
215 #define NIC_CR_RD0 0x08 /*!< \brief Remote DMA command bit 0 */
216 #define NIC_CR_RD1 0x10 /*!< \brief Remote DMA command bit 1 */
217 #define NIC_CR_RD2 0x20 /*!< \brief Remote DMA command bit 2 */
218 #define NIC_CR_PS0 0x40 /*!< \brief Page select bit 0 */
219 #define NIC_CR_PS1 0x80 /*!< \brief Page select bit 1 */
220 
221 /*
222  * Interrupt status register bits.
223  */
224 #define NIC_ISR_PRX 0x01 /*!< \brief Packet received */
225 #define NIC_ISR_PTX 0x02 /*!< \brief Packet transmitted */
226 #define NIC_ISR_RXE 0x04 /*!< \brief Receive error */
227 #define NIC_ISR_TXE 0x08 /*!< \brief Transmit error */
228 #define NIC_ISR_OVW 0x10 /*!< \brief Overwrite warning */
229 #define NIC_ISR_CNT 0x20 /*!< \brief Counter overflow */
230 #define NIC_ISR_RDC 0x40 /*!< \brief Remote DMA complete */
231 #define NIC_ISR_RST 0x80 /*!< \brief Reset status */
232 
233 /*
234  * Interrupt mask register bits.
235  */
236 #define NIC_IMR_PRXE 0x01 /*!< \brief Packet received interrupt enable */
237 #define NIC_IMR_PTXE 0x02 /*!< \brief Packet transmitted interrupt enable */
238 #define NIC_IMR_RXEE 0x04 /*!< \brief Receive error interrupt enable */
239 #define NIC_IMR_TXEE 0x08 /*!< \brief Transmit error interrupt enable */
240 #define NIC_IMR_OVWE 0x10 /*!< \brief Overwrite warning interrupt enable */
241 #define NIC_IMR_CNTE 0x20 /*!< \brief Counter overflow interrupt enable */
242 #define NIC_IMR_RCDE 0x40 /*!< \brief Remote DMA complete interrupt enable */
243 
244 /*
245  * Data configuration register bits.
246  */
247 #define NIC_DCR_WTS 0x01 /*!< \brief Word transfer select */
248 #define NIC_DCR_BOS 0x02 /*!< \brief Byte order select */
249 #define NIC_DCR_LAS 0x04 /*!< \brief Long address select */
250 #define NIC_DCR_LS 0x08 /*!< \brief Loopback select */
251 #define NIC_DCR_AR 0x10 /*!< \brief Auto-initialize remote */
252 #define NIC_DCR_FT0 0x20 /*!< \brief FIFO threshold select bit 0 */
253 #define NIC_DCR_FT1 0x40 /*!< \brief FIFO threshold select bit 1 */
254 
255 /*
256  * Transmit configuration register bits.
257  */
258 #define NIC_TCR_CRC 0x01 /*!< \brief Inhibit CRC */
259 #define NIC_TCR_LB0 0x02 /*!< \brief Encoded loopback control bit 0 */
260 #define NIC_TCR_LB1 0x04 /*!< \brief Encoded loopback control bit 1 */
261 #define NIC_TCR_ATD 0x08 /*!< \brief Auto transmit disable */
262 #define NIC_TCR_OFST 0x10 /*!< \brief Collision offset enable */
263 
264 /*
265  * Transmit status register bits.
266  */
267 #define NIC_TSR_PTX 0x01 /*!< \brief Packet transmitted */
268 #define NIC_TSR_COL 0x04 /*!< \brief Transmit collided */
269 #define NIC_TSR_ABT 0x08 /*!< \brief Transmit aborted */
270 #define NIC_TSR_CRS 0x10 /*!< \brief Carrier sense lost */
271 #define NIC_TSR_FU 0x20 /*!< \brief FIFO underrun */
272 #define NIC_TSR_CDH 0x40 /*!< \brief CD heartbeat */
273 #define NIC_TSR_OWC 0x80 /*!< \brief Out of window collision */
274 
275 /*
276  * Receive configuration register bits.
277  */
278 #define NIC_RCR_SEP 0x01 /*!< \brief Save errored packets */
279 #define NIC_RCR_AR 0x02 /*!< \brief Accept runt packets */
280 #define NIC_RCR_AB 0x04 /*!< \brief Accept broadcast */
281 #define NIC_RCR_AM 0x08 /*!< \brief Accept multicast */
282 #define NIC_RCR_PRO 0x10 /*!< \brief Promiscuous physical */
283 #define NIC_RCR_MON 0x20 /*!< \brief Monitor mode */
284 
285 /*
286  * Receive status register bits.
287  */
288 #define NIC_RSR_PRX 0x01 /*!< \brief Packet received intact */
289 #define NIC_RSR_CRC 0x02 /*!< \brief CRC error */
290 #define NIC_RSR_FAE 0x04 /*!< \brief Frame alignment error */
291 #define NIC_RSR_FO 0x08 /*!< \brief FIFO overrun */
292 #define NIC_RSR_MPA 0x10 /*!< \brief Missed packet */
293 #define NIC_RSR_PHY 0x20 /*!< \brief Physical/multicast address */
294 #define NIC_RSR_DIS 0x40 /*!< \brief Receiver disabled */
295 #define NIC_RSR_DFR 0x80 /*!< \brief Deferring */
296 
297 /*
298  * EEPROM command register bits.
299  */
300 #define NIC_EECR_EEM1 0x80 /*!< \brief EEPROM Operating Mode */
301 #define NIC_EECR_EEM0 0x40 /*!< \brief EEPROM Operating Mode
302  - 0 0 Normal operation
303  - 0 1 Auto-load
304  - 1 0 9346 programming
305  - 1 1 Config register write enab */
306 #define NIC_EECR_EECS 0x08 /*!< \brief EEPROM Chip Select */
307 #define NIC_EECR_EESK 0x04 /*!< \brief EEPROM Clock */
308 #define NIC_EECR_EEDI 0x02 /*!< \brief EEPROM Data In */
309 #define NIC_EECR_EEDO 0x01 /*!< \brief EEPROM Data Out */
310 
311 /*
312  * Configuration register 2 bits.
313  */
314 #define NIC_CONFIG2_PL1 0x80 /*!< \brief Network media type */
315 #define NIC_CONFIG2_PL0 0x40 /*!< \brief Network media type
316  - 0 0 TP/CX auto-detect
317  - 0 1 10baseT
318  - 1 0 10base5
319  - 1 1 10base2 */
320 #define NIC_CONFIG2_BSELB 0x20 /*!< \brief BROM disable */
321 #define NIC_CONFIG2_BS4 0x10 /*!< \brief BROM size/base */
322 #define NIC_CONFIG2_BS3 0x08
323 #define NIC_CONFIG2_BS2 0x04
324 #define NIC_CONFIG2_BS1 0x02
325 #define NIC_CONFIG2_BS0 0x01
326 
327 /*
328  * Configuration register 3 bits
329  */
330 #define NIC_CONFIG3_PNP 0x80 /*!< \brief PnP Mode */
331 #define NIC_CONFIG3_FUDUP 0x40 /*!< \brief Full duplex */
332 #define NIC_CONFIG3_LEDS1 0x20 /*!< \brief LED1/2 pin configuration
333  - 0 LED1 == LED_RX, LED2 == LED_TX
334  - 1 LED1 == LED_CRS, LED2 == MCSB */
335 #define NIC_CONFIG3_LEDS0 0x10 /*!< \brief LED0 pin configration
336  - 0 LED0 pin == LED_COL
337  - 1 LED0 pin == LED_LINK */
338 #define NIC_CONFIG3_SLEEP 0x04 /*!< \brief Sleep mode */
339 #define NIC_CONFIG3_PWRDN 0x02 /*!< \brief Power Down */
340 #define NIC_CONFIG3_ACTIVEB 0x01 /*!< \brief inverse of bit 0 in PnP Act Reg */
341 
342 /*@}*/
343 
344 /*!
345  * \brief Read byte from controller register.
346  */
347 #define nic_read(reg) *(base + (reg))
348 
349 /*!
350  * \brief Write byte to controller register.
351  */
352 #define nic_write(reg, data) *(base + (reg)) = data
353 
354 #endif
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