59 #include <avr/interrupt.h>
60 #include <util/crc16.h>
61 #include "contiki-conf.h"
65 #define TRIG1 DDRB |= 0x04, PINB |= 0x04
66 #define TRIG2 DDRD |= 0x80, PIND |= 0x80
88 #if RCB_REVISION == RCB_B
93 # define MOSIPIN (0x02)
94 # define MISOPIN (0x03)
95 # define SCKPIN (0x01)
97 # define RSTPIN (0x05)
99 # define IRQPIN (0x04)
101 # define SLPTRPIN (0x04)
103 # define USARTVECT USART1_RX_vect
105 # define HAS_SPARE_TIMER
107 #elif HARWARE_REVISION == ZIGBIT
110 # define SSPIN (0x00)
112 # define MOSIPIN (0x02)
113 # define MISOPIN (0x03)
114 # define SCKPIN (0x01)
116 # define RSTPIN (0x07)
118 # define IRQPIN (0x05)
120 # define SLPTRPIN (0x04)
122 # define TXCWPIN (0x07)
124 # define USARTVECT USART1_RX_vect
129 #elif RAVEN_REVISION == RAVEN_D
132 # define SSPIN (0x04)
134 # define MOSIPIN (0x05)
135 # define MISOPIN (0x06)
136 # define SCKPIN (0x07)
138 # define RSTPIN (0x01)
140 # define IRQPIN (0x06)
142 # define SLPTRPIN (0x03)
144 # define TXCWPIN (0x00)
146 # define USARTVECT USART1_RX_vect
149 # define HAS_SPARE_TIMER
151 #elif RAVEN_REVISION == RAVENUSB_C
154 # define SSPIN (0x00)
156 # define MOSIPIN (0x02)
157 # define MISOPIN (0x03)
158 # define SCKPIN (0x01)
160 # define RSTPIN (0x05)
162 # define IRQPIN (0x04)
164 # define SLPTRPIN (0x04)
166 # define TXCWPIN (0x07)
168 # define USARTVECT USART1_RX_vect
171 # define HAS_SPARE_TIMER
173 #elif HARWARE_REVISION == IRIS
176 # define SSPIN (0x00)
178 # define MOSIPIN (0x02)
179 # define MISOPIN (0x03)
180 # define SCKPIN (0x01)
182 # define RSTPIN (0x06)
184 # define IRQPIN (0x04)
186 # define SLPTRPIN (0x07)
190 # define USARTVECT USART1_RX_vect
195 #error "Platform undefined in hal.h"
210 #define CAT(x, y) x##y
211 #define CAT2(x, y, z) x##y##z
212 #define DDR(x) CAT(DDR, x)
213 #define PORT(x) CAT(PORT, x)
214 #define PIN(x) CAT(PIN, x)
215 #define UCSR(num, let) CAT2(UCSR,num,let)
216 #define RXEN(x) CAT(RXEN,x)
217 #define TXEN(x) CAT(TXEN,x)
218 #define TXC(x) CAT(TXC,x)
219 #define RXC(x) CAT(RXC,x)
220 #define RXCIE(x) CAT(RXCIE,x)
221 #define UCSZ(x,y) CAT2(UCSZ,x,y)
222 #define UBRR(x,y) CAT2(UBRR,x,y)
223 #define UDRE(x) CAT(UDRE,x)
224 #define UDRIE(x) CAT(UDRIE,x)
225 #define UDR(x) CAT(UDR,x)
226 #define TCNT(x) CAT(TCNT,x)
227 #define TIMSK(x) CAT(TIMSK,x)
228 #define TCCR(x,y) CAT2(TCCR,x,y)
229 #define COM(x,y) CAT2(COM,x,y)
230 #define OCR(x,y) CAT2(OCR,x,y)
231 #define CS(x,y) CAT2(CS,x,y)
232 #define WGM(x,y) CAT2(WGM,x,y)
233 #define OCIE(x,y) CAT2(OCIE,x,y)
234 #define COMPVECT(x) CAT2(TIMER,x,_COMPA_vect)
235 #define UDREVECT(x) CAT2(USART,x,_UDRE_vect)
236 #define RXVECT(x) CAT2(USART,x,_RX_vect)
245 #define SLP_TR SLPTRPIN
246 #define DDR_SLP_TR DDR( SLPTRPORT )
247 #define PORT_SLP_TR PORT( SLPTRPORT )
248 #define PIN_SLP_TR PIN( SLPTRPORT )
249 #define hal_set_slptr_high( ) ( PORT_SLP_TR |= ( 1 << SLP_TR ) )
250 #define hal_set_slptr_low( ) ( PORT_SLP_TR &= ~( 1 << SLP_TR ) )
251 #define hal_get_slptr( ) ( ( PIN_SLP_TR & ( 1 << SLP_TR ) ) >> SLP_TR )
253 #define DDR_RST DDR( RSTPORT )
254 #define PORT_RST PORT( RSTPORT )
255 #define PIN_RST PIN( RSTPORT )
256 #define hal_set_rst_high( ) ( PORT_RST |= ( 1 << RST ) )
257 #define hal_set_rst_low( ) ( PORT_RST &= ~( 1 << RST ) )
258 #define hal_get_rst( ) ( ( PIN_RST & ( 1 << RST ) ) >> RST )
259 #define HAL_SS_PIN SSPIN
260 #define HAL_PORT_SPI PORT( SPIPORT )
261 #define HAL_DDR_SPI DDR( SPIPORT )
262 #define HAL_DD_SS SSPIN
263 #define HAL_DD_SCK SCKPIN
264 #define HAL_DD_MOSI MOSIPIN
265 #define HAL_DD_MISO MISOPIN
269 #define HAL_SS_HIGH( ) (HAL_PORT_SPI |= ( 1 << HAL_SS_PIN ))
270 #define HAL_SS_LOW( ) (HAL_PORT_SPI &= ~( 1 << HAL_SS_PIN ))
279 #if ( F_CPU == 16000000UL )
280 #define HAL_TCCR1B_CONFIG ( ( 1 << ICES1 ) | ( 1 << CS12 ) )
281 #define HAL_US_PER_SYMBOL ( 1 )
282 #define HAL_SYMBOL_MASK ( 0xFFFFffff )
283 #elif ( F_CPU == 8000000UL )
284 #define HAL_TCCR1B_CONFIG ( ( 1 << ICES1 ) | ( 1 << CS11 ) | ( 1 << CS10 ) )
285 #define HAL_US_PER_SYMBOL ( 2 )
286 #define HAL_SYMBOL_MASK ( 0x7FFFffff )
287 #elif ( F_CPU == 4000000UL )
288 #define HAL_TCCR1B_CONFIG ( ( 1 << ICES1 ) | ( 1 << CS11 ) | ( 1 << CS10 ) )
289 #define HAL_US_PER_SYMBOL ( 1 )
290 #define HAL_SYMBOL_MASK ( 0xFFFFffff )
291 #elif ( F_CPU == 1000000UL )
292 #define HAL_TCCR1B_CONFIG ( ( 1 << ICES1 ) | ( 1 << CS11 ) )
293 #define HAL_US_PER_SYMBOL ( 2 )
294 #define HAL_SYMBOL_MASK ( 0x7FFFffff )
296 #error "Clock speed not supported."
299 #if HARWARE_REVISION == ZIGBIT
301 #define RADIO_VECT INT5_vect
302 #define HAL_ENABLE_RADIO_INTERRUPT( ) { ( EIMSK |= ( 1 << INT5 ) ) ; EICRB |= 0x0C ; PORTE &= ~(1<<PE5); DDRE &= ~(1<<DDE5); }
303 #define HAL_DISABLE_RADIO_INTERRUPT( ) ( EIMSK &= ~( 1 << INT5 ) )
305 #define RADIO_VECT TIMER1_CAPT_vect
306 #define HAL_ENABLE_RADIO_INTERRUPT( ) ( TIMSK1 |= ( 1 << ICIE1 ) )
307 #define HAL_DISABLE_RADIO_INTERRUPT( ) ( TIMSK1 &= ~( 1 << ICIE1 ) )
310 #define HAL_ENABLE_OVERFLOW_INTERRUPT( ) ( TIMSK1 |= ( 1 << TOIE1 ) )
311 #define HAL_DISABLE_OVERFLOW_INTERRUPT( ) ( TIMSK1 &= ~( 1 << TOIE1 ) )
314 #define AVR_ENTER_CRITICAL_REGION( ) {uint8_t volatile saved_sreg = SREG; cli( )
318 #define AVR_LEAVE_CRITICAL_REGION( ) SREG = saved_sreg;}
323 #define hal_enable_trx_interrupt( ) HAL_ENABLE_RADIO_INTERRUPT( )
329 #define hal_disable_trx_interrupt( ) HAL_DISABLE_RADIO_INTERRUPT( )
336 #define HAL_BAT_LOW_MASK ( 0x80 )
337 #define HAL_TRX_UR_MASK ( 0x40 )
338 #define HAL_TRX_END_MASK ( 0x08 )
339 #define HAL_RX_START_MASK ( 0x04 )
340 #define HAL_PLL_UNLOCK_MASK ( 0x02 )
341 #define HAL_PLL_LOCK_MASK ( 0x01 )
343 #define HAL_MIN_FRAME_LENGTH ( 0x03 )
344 #define HAL_MAX_FRAME_LENGTH ( 0x7F )
365 typedef void (*rx_callback_t) (uint16_t data);
392 void hal_sram_read( uint8_t address, uint8_t length, uint8_t *data );
393 void hal_sram_write( uint8_t address, uint8_t length, uint8_t *data );