Contiki 2.5
dma.h
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1 /**
2  * \file
3  * DMA driver header
4  * \author
5  * Original: Martti Huttunen <martti@sensinode.com>
6  * Port: Zach Shelby <zach@sensinode.com>
7  */
8 
9 #ifndef __DMA_H
10 #define __DMA_H
11 #include "banked.h"
12 #include "cc2430_sfr.h"
13 
14 /** DMA triggers */
15 typedef enum dma_trigger_t
16 {
17  DMA_T_NONE=0, /*!<DMA No trigger, setting DMAREQ.DMAREQx bit starts transfer*/
18  DMA_T_PREV=1, /*!<DMA DMA channel is triggered by completion of previous channel*/
19  DMA_T_T1_CH0=2, /*!<Timer 1 Timer 1, compare, channel 0*/
20  DMA_T_T1_CH1=3, /*!<Timer 1 Timer 1, compare, channel 1*/
21  DMA_T_T1_CH2=4, /*!<Timer 1 Timer 1, compare, channel 2*/
22  DMA_T_T2_COMP=5, /*!<Timer 2 Timer 2, compare*/
23  DMA_T_T2_OVFL=6, /*!<Timer 2 Timer 2, overflow*/
24  DMA_T_T3_CH0=7, /*!<Timer 3 Timer 3, compare, channel 0*/
25  DMA_T_T3_CH1=8, /*!<Timer 3 Timer 3, compare, channel 1*/
26  DMA_T_T4_CH0=9, /*!<Timer 4 Timer 4, compare, channel 0*/
27  DMA_T_T4_CH1=10, /*!<Timer 4 Timer 4, compare, channel 1*/
28  DMA_T_ST=11, /*!<Sleep Timer Sleep Timer compare*/
29  DMA_T_IOC_0=12, /*!<IO Controller Port 0 I/O pin input transition*/
30  DMA_T_IOC_1=13, /*!<IO Controller Port 1 I/O pin input transition*/
31  DMA_T_URX0=14, /*!<USART0 USART0 RX complete*/
32  DMA_T_UTX0=15, /*!<USART0 USART0 TX complete*/
33  DMA_T_URX1=16, /*!<USART1 USART1 RX complete*/
34  DMA_T_UTX1=17, /*!<USART1 USART1 TX complete*/
35  DMA_T_FLASH=18, /*!<Flash controller Flash data write complete*/
36  DMA_T_RADIO=19, /*!<Radio RF packet byte received/transmit*/
37  DMA_T_ADC_CHALL=20, /*!<ADC ADC end of a conversion in a sequence, sample ready*/
38  DMA_T_ADC_CH11=21, /*!<ADC ADC end of conversion channel 0 in sequence, sample ready*/
39  DMA_T_ADC_CH21=22, /*!<ADC ADC end of conversion channel 1 in sequence, sample ready*/
40  DMA_T_ADC_CH32=23, /*!<ADC ADC end of conversion channel 2 in sequence, sample ready*/
41  DMA_T_ADC_CH42=24, /*!<ADC ADC end of conversion channel 3 in sequence, sample ready*/
42  DMA_T_ADC_CH53=25, /*!<ADC ADC end of conversion channel 4 in sequence, sample ready*/
43  DMA_T_ADC_CH63=26, /*!<ADC ADC end of conversion channel 5 in sequence, sample ready*/
44  DMA_T_ADC_CH74=27, /*!<ADC ADC end of conversion channel 6 in sequence, sample ready*/
45  DMA_T_ADC_CH84=28, /*!<ADC ADC end of conversion channel 7 in sequence, sample ready*/
46  DMA_T_ENC_DW=29, /*!<AES AES encryption processor requests download input data*/
47  DMA_T_ENC_UP=30, /*!<AES AES encryption processor requests upload output data*/
48  DMA_T_RES=31
49 }dma_trigger_t;
50 
51 /** variable DMA length modes */
52 typedef enum dma_vlen_t
53 {
54  DMA_VLEN_LEN = (0 << 5),/*!<Use LEN for transfer count*/
55  DMA_VLEN_N1 = (1 << 5),/*!<Transfer the number of bytes/words specified by first byte/word + 1 (up to a maximum specified by LEN). Thus transfer count excludes length byte/word.*/
56  DMA_VLEN_N = (2 << 5),/*!<Transfer the number of bytes/words specified by first byte/word (up to a maximum specified by LEN). Thus transfer count includes length byte/word.*/
57  DMA_VLEN_N2 = (3 << 5),/*!<Transfer the number of bytes/words specified by first byte/word + 2 (up to a maximum specified by LEN).*/
58  DMA_VLEN_N3 = (4 << 5),/*!<Transfer the number of bytes/words specified by first byte/word + 3 (up to a maximum specified by LEN).*/
59  DMA_VLEN_RES1 = (5 << 5),/*!<reserved*/
60  DMA_VLEN_RES2 = (6 << 5),/*!<reserved*/
61  DMA_VLEN_LEN2 = (7 << 5) /*!<Use LEN for transfer count*/
62 }dma_vlen_t;
63 
64 /** address increment modes */
65 typedef enum dma_inc_t
66 {
67  DMA_NOINC = 0, /*!<No increment*/
68  DMA_INC = 1, /*!<Increment*/
69  DMA_INC2 = 2, /*!<Increment 2*/
70  DMA_DEC = 3 /*!<Decrement*/
71 }dma_inc_t;
72 
73 /** transfer types */
74 typedef enum dma_type_t
75 {
76  DMA_SINGLE = 0, /*!<Single*/
77  DMA_BLOCK = 1, /*!<Block*/
78  DMA_RPT = 2, /*!<Repeated single*/
79  DMA_BLOCK_RPT=3 /*!<Repeated block*/
80 }dma_type_t;
81 
82 /** DMA configuration structure */
83 typedef struct dma_config_t
84 {
85  uint8_t src_h; /*!<source address high byte*/
86  uint8_t src_l; /*!<source address low byte*/
87  uint8_t dst_h; /*!<dest. address high byte*/
88  uint8_t dst_l; /*!<dest. address low byte*/
89  uint8_t len_h; /*!<transfer mode in high 3 bits, length high byte, 4 lowest bits*/
90  uint8_t len_l; /*!<length low byte*/
91  uint8_t t_mode; /*!<transfer mode: bit7=word mode, 6-5=block/single 4-0=trigger */
92  uint8_t addr_mode; /*!<address mode: 7-6=src inc, 5-4=dst_inc, 3=IRQ, 2=M8(vlen) 1-0:priority*/
93 
94 }dma_config_t;
95 
96 extern void dma_init(void) __banked;
97 typedef void (*dma_func)(void *);
98 
99 extern dma_config_t dma_conf[4];
100 
101 #ifdef HAVE_DMA
102 typedef uint8_t xDMAHandle;
103 
104 #define dma_config(channel, src, src_inc, dst, dst_inc, length, vlen_mode, t_mode, trigger, proc) dma_config2(channel,src,src_inc, dst, dst_inc, length, 0, vlen_mode, t_mode, trigger, proc)
105 /*
106  extern xDMAHandle dma_config(uint8_t channel, void *src, dma_inc_t src_inc, void *dst, dma_inc_t dst_inc,
107  uint16_t length, dma_vlen_t vlen_mode, dma_type_t t_mode,
108  dma_trigger_t trigger, struct process * p);
109 */
110 extern xDMAHandle dma_config2(uint8_t channel, void *src, dma_inc_t src_inc, void *dst, dma_inc_t dst_inc,
111  uint16_t length, uint8_t word_mode, dma_vlen_t vlen_mode, dma_type_t t_mode,
112  dma_trigger_t trigger, struct process * p) __banked;
113 extern uint8_t dma_arm(xDMAHandle channel) __banked;
114 extern uint8_t dma_abort(xDMAHandle channel) __banked;
115 extern uint8_t dma_trigger(xDMAHandle channel) __banked;
116 extern uint8_t dma_state(xDMAHandle channel) __banked;
117 void dma_config_print(xDMAHandle channel) __banked;
118 #endif
119 
120 extern void dma_ISR( void ) __interrupt (DMA_VECTOR);
121 
122 #endif /*__DMA_H*/
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