Contiki 2.5
isr.h
1 /*
2  * Copyright (c) 2010, Mariano Alvira <mar@devl.org> and other contributors
3  * to the MC1322x project (http://mc1322x.devl.org)
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  * notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the distribution.
14  * 3. Neither the name of the Institute nor the names of its contributors
15  * may be used to endorse or promote products derived from this software
16  * without specific prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28  * SUCH DAMAGE.
29  *
30  * This file is part of libmc1322x: see http://mc1322x.devl.org
31  * for details.
32  *
33  *
34  */
35 
36 #ifndef ISR_H
37 #define ISR_H
38 
39 #define INTBASE (0x80020000)
40 
41 #include <stdint.h>
42 
43 /* Structure-based ITC access */
44 #define __INTERRUPT_union(x) \
45  union { \
46  uint32_t x; \
47  struct ITC_##x { \
48  uint32_t ASM:1; \
49  uint32_t UART1:1; \
50  uint32_t UART2:1; \
51  uint32_t CRM:1; \
52  uint32_t I2C:1; \
53  uint32_t TMR:1; \
54  uint32_t SPIF:1; \
55  uint32_t MACA:1; \
56  uint32_t SSI:1; \
57  uint32_t ADC:1; \
58  uint32_t SPI:1; \
59  uint32_t :21; \
60  } x##bits; \
61  };
62 
63 struct ITC_struct {
64  union {
65  uint32_t INTCNTL;
66  struct ITC_INTCNTL {
67  uint32_t :19;
68  uint32_t FIAD:1;
69  uint32_t NIAD:1;
70  uint32_t :11;
71  } INTCNTLbits;
72  };
73  uint32_t NIMASK;
74  uint32_t INTENNUM;
75  uint32_t INTDISNUM;
76  __INTERRUPT_union(INTENABLE);
77  __INTERRUPT_union(INTTYPE);
78  uint32_t reserved[4];
79  uint32_t NIVECTOR;
80  uint32_t FIVECTOR;
81  __INTERRUPT_union(INTSRC);
82  __INTERRUPT_union(INTFRC);
83  __INTERRUPT_union(NIPEND);
84  __INTERRUPT_union(FIPEND);
85 };
86 #undef __INTERRUPT_union
87 
88 static volatile struct ITC_struct * const ITC = (void *) (INTBASE);
89 
90 
91 /* Old register definitions, for compatibility */
92 #ifndef REG_NO_COMPAT
93 
94 #define INTCNTL_OFF (0x0)
95 #define INTENNUM_OFF (0x8)
96 #define INTDISNUM_OFF (0xC)
97 #define INTENABLE_OFF (0x10)
98 #define INTSRC_OFF (0x30)
99 #define INTFRC_OFF (0x34)
100 #define NIPEND_OFF (0x38)
101 
102 static volatile uint32_t * const INTCNTL = ((volatile uint32_t *) (INTBASE + INTCNTL_OFF));
103 static volatile uint32_t * const INTENNUM = ((volatile uint32_t *) (INTBASE + INTENNUM_OFF));
104 static volatile uint32_t * const INTDISNUM = ((volatile uint32_t *) (INTBASE + INTDISNUM_OFF));
105 static volatile uint32_t * const INTENABLE = ((volatile uint32_t *) (INTBASE + INTENABLE_OFF));
106 static volatile uint32_t * const INTSRC = ((volatile uint32_t *) (INTBASE + INTSRC_OFF));
107 static volatile uint32_t * const INTFRC = ((volatile uint32_t *) (INTBASE + INTFRC_OFF));
108 static volatile uint32_t * const NIPEND = ((volatile uint32_t *) (INTBASE + NIPEND_OFF));
109 
110 enum interrupt_nums {
111  INT_NUM_ASM = 0,
112  INT_NUM_UART1,
113  INT_NUM_UART2,
114  INT_NUM_CRM,
115  INT_NUM_I2C,
116  INT_NUM_TMR,
117  INT_NUM_SPIF,
118  INT_NUM_MACA,
119  INT_NUM_SSI,
120  INT_NUM_ADC,
121  INT_NUM_SPI,
122 };
123 
124 #define global_irq_disable() (set_bit(*INTCNTL,20))
125 #define global_irq_enable() (clear_bit(*INTCNTL,20))
126 
127 #define enable_irq(irq) (*INTENNUM = INT_NUM_##irq)
128 #define disable_irq(irq) (*INTDISNUM = INT_NUM_##irq)
129 
130 #define safe_irq_disable(x) volatile uint32_t saved_irq; saved_irq = *INTENABLE; disable_irq(x)
131 #define irq_restore() *INTENABLE = saved_irq
132 
133 #endif /* REG_NO_COMPAT */
134 
135 /* Macro to safely disable all interrupts for a block of code.
136  Use it like this:
137  disable_int({
138  asdf = 1234;
139  printf("hi\r\n");
140  });
141 */
142 #define __int_top() volatile uint32_t saved_intenable
143 #define __int_disable() saved_intenable = ITC->INTENABLE; ITC->INTENABLE = 0
144 #define __int_enable() ITC->INTENABLE = saved_intenable
145 #define disable_int(x) do { \
146  __int_top(); \
147  __int_disable(); \
148  x; \
149  __int_enable(); } while(0)
150 
151 
152 extern void tmr0_isr(void) __attribute__((weak));
153 extern void tmr1_isr(void) __attribute__((weak));
154 extern void tmr2_isr(void) __attribute__((weak));
155 extern void tmr3_isr(void) __attribute__((weak));
156 
157 extern void rtc_isr(void) __attribute__((weak));
158 extern void kbi4_isr(void) __attribute__((weak));
159 extern void kbi5_isr(void) __attribute__((weak));
160 extern void kbi6_isr(void) __attribute__((weak));
161 extern void kbi7_isr(void) __attribute__((weak));
162 
163 extern void cal_isr(void) __attribute__((weak));
164 
165 extern void uart1_isr(void) __attribute__((weak));
166 extern void uart2_isr(void) __attribute__((weak));
167 
168 extern void maca_isr(void) __attribute__((weak));
169 
170 extern void asm_isr(void) __attribute__((weak));
171 
172 extern void i2c_isr(void) __attribute__((weak));
173 
174 #endif
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