Contiki 2.5
maca.h
1 /*
2  * Copyright (c) 2010, Mariano Alvira <mar@devl.org> and other contributors
3  * to the MC1322x project (http://mc1322x.devl.org)
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  * notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the distribution.
14  * 3. Neither the name of the Institute nor the names of its contributors
15  * may be used to endorse or promote products derived from this software
16  * without specific prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28  * SUCH DAMAGE.
29  *
30  * This file is part of libmc1322x: see http://mc1322x.devl.org
31  * for details.
32  *
33  *
34  */
35 
36 #ifndef _MACA_H_
37 #define _MACA_H_
38 
39 #include <packet.h>
40 #include <stdint.h>
41 #include <utils.h>
42 
43 /* maca initialization and on off routines */
44 void maca_init(void);
45 void maca_off(void);
46 void maca_on(void);
47 
48 /* run periodically to make sure the maca is still doing right */
49 void check_maca(void);
50 
51 /* maca configuration interface */
52 void set_power(uint8_t power);
53 void set_channel(uint8_t chan);
54 
55 extern uint8_t (*get_lqi)(void);
56 
57 #define DEMOD_DCD 1 /* -96dBm, 22.2mA */
58 #define DEMOD_NCD 0 /* -100dBm, 24.2mA */
59 void set_demodulator_type(uint8_t demod);
60 
61 /* set_fcs_mode(NO_FCS) to disable checksum filtering */
62 extern volatile uint8_t fcs_mode;
63 #define set_fcs_mode(x) fcs_mode = (x)
64 
65 /* set_prm_mode(PROMISC) to disable address filtering */
66 /* set_prm_mode(AUTOACK) to enable address filtering AND autoack */
67 extern volatile uint8_t prm_mode;
68 #define set_prm_mode(x) prm_mode = (x)
69 
70 /* maca packet interface */
71 void tx_packet(volatile packet_t *p);
72 volatile packet_t* rx_packet(void);
73 volatile packet_t* get_free_packet(void);
74 void free_packet(volatile packet_t *p);
75 void free_all_packets(void);
76 
77 extern volatile packet_t *rx_head, *tx_head;
78 extern volatile uint32_t maca_entry;
79 
80 extern void maca_rx_callback(volatile packet_t *p) __attribute__((weak));
81 extern void maca_tx_callback(volatile packet_t *p) __attribute__((weak));
82 
83 /* maca lowlevel routines */
84 /* most applications won't need to use them */
85 void reset_maca(void);
86 void init_phy(void);
87 void flyback_init(void);
88 void ResumeMACASync(void);
89 void radio_init(void);
90 uint32_t init_from_flash(uint32_t addr);
91 
92 #define MAX_PACKET_SIZE (MAX_PAYLOAD_SIZE + 2) /* packet includes 2 bytes of checksum */
93 
94 /* maca register and field defines */
95 
96 #define MACA_BASE (0x80004000)
97 #define MACA_RESET ((volatile uint32_t *) (MACA_BASE+0x04))
98 #define MACA_RANDOM ((volatile uint32_t *) (MACA_BASE+0x08))
99 #define MACA_CONTROL ((volatile uint32_t *) (MACA_BASE+0x0c))
100 
101 /* MACA_CONTROL bits and fields */
102 #define ISM 20
103 #define PRECOUNT 16 /* preamble reapeat counter */
104 #define PRECOUNT_MASK bit_mask(4,PRECOUNT)
105 #define RTSO 15 /* reset slot counter */
106 #define ROLE 13 /* set if PAN coordinator */
107 #define NOFC 12 /* set to disable FCS */
108 enum {
109  USE_FCS = 0,
110  NO_FCS = 1,
111 };
112 #define PRM 11 /* set for promiscuous mode */
113 enum {
114  AUTOACK = 0,
115  PROMISC = 1,
116 };
117 #define REL 10 /* 1 for relative, 0 for absolute */
118 #define ASAP 9 /* 1 start now, 0 timer start */
119 #define BCN 8 /* 1 beacon only, 0 for a */
120 #define AUTO 7 /* 1 continuous rx, rx only once */
121 #define LFSR 6 /* 1 use polynomial for Turbolink */
122 #define TM 5
123 
124 #define MACA_MODE 3
125 #define MODE_MASK bit_mask(2,MACA_MODE)
126 #define NO_CCA 0
127 #define NO_SLOT_CCA 1
128 #define SLOT_CCA 2
129 
130 #define SEQUENCE 0
131 #define SEQUENCE_MASK bit_mask(3,SEQUENCE)
132 /* end of MACA_CONTROL bits and fields */
133 
134 #define MACA_STATUS ((volatile uint32_t *) (MACA_BASE+0x10))
135 /* MACA_STATUS bits and fields */
136 #define STATUS_TIMEOUT 15
137 #define CRC 14
138 #define BUSY 13
139 #define OVR 12
140 #define CODE 0
141 #define CODE_MASK bit_mask(4,CODE)
142 /* status codes */
143 #define SUCCESS 0
144 #define CODE_TIMEOUT 1
145 #define CHANNEL_BUSY 2
146 #define CRC_FAILED 3
147 #define ABORTED 4
148 #define NO_ACK 5
149 #define NO_DATA 6
150 #define LATE_START 7
151 #define EXT_TIMEOUT 8
152 #define EXT_PND_TIMEOUT 9
153 #define PLL_UNLOCK 12
154 #define EXTERNAL_ABORT 13
155 #define NOT_COMPLETED 14
156 #define DMA_BUS_ERROR 15
157 /* end of MACA_CONTROL bits and fields */
158 
159 #define MACA_FRMPND ((volatile uint32_t *) (MACA_BASE+0x14))
160 #define MACA_TMREN ((volatile uint32_t *) (MACA_BASE+0x40))
161 #define MACA_TMRDIS ((volatile uint32_t *) (MACA_BASE+0x44))
162 #define MACA_CLK ((volatile uint32_t *) (MACA_BASE+0x48))
163 #define MACA_STARTCLK ((volatile uint32_t *) (MACA_BASE+0x4c))
164 #define MACA_CPLCLK ((volatile uint32_t *) (MACA_BASE+0x50))
165 #define MACA_SFTCLK ((volatile uint32_t *) (MACA_BASE+0x54))
166 #define MACA_CLKOFFSET ((volatile uint32_t *) (MACA_BASE+0x58))
167 #define MACA_RELCLK ((volatile uint32_t *) (MACA_BASE+0x5c))
168 #define MACA_CPLTIM ((volatile uint32_t *) (MACA_BASE+0x60))
169 #define MACA_SLOTOFFSET ((volatile uint32_t *) (MACA_BASE+0x64))
170 #define MACA_TIMESTAMP ((volatile uint32_t *) (MACA_BASE+0x68))
171 #define MACA_DMARX ((volatile uint32_t *) (MACA_BASE+0x80))
172 #define MACA_DMATX ((volatile uint32_t *) (MACA_BASE+0x84))
173 #define MACA_DMAPOLL ((volatile uint32_t *) (MACA_BASE+0x88))
174 #define MACA_TXLEN ((volatile uint32_t *) (MACA_BASE+0x8c))
175 #define MACA_TXSEQNR ((volatile uint32_t *) (MACA_BASE+0x90))
176 #define MACA_SETRXLVL ((volatile uint32_t *) (MACA_BASE+0x94))
177 #define MACA_GETRXLVL ((volatile uint32_t *) (MACA_BASE+0x98))
178 #define MACA_IRQ ((volatile uint32_t *) (MACA_BASE+0xc0))
179 #define MACA_CLRIRQ ((volatile uint32_t *) (MACA_BASE+0xc4))
180 #define MACA_SETIRQ ((volatile uint32_t *) (MACA_BASE+0xc8))
181 #define MACA_MASKIRQ ((volatile uint32_t *) (MACA_BASE+0xcc))
182 #define MACA_MACPANID ((volatile uint32_t *) (MACA_BASE+0x100))
183 #define MACA_MAC16ADDR ((volatile uint32_t *) (MACA_BASE+0x104))
184 #define MACA_MAC64HI ((volatile uint32_t *) (MACA_BASE+0x108))
185 #define MACA_MAC64LO ((volatile uint32_t *) (MACA_BASE+0x10c))
186 #define MACA_FLTREJ ((volatile uint32_t *) (MACA_BASE+0x110))
187 #define MACA_CLKDIV ((volatile uint32_t *) (MACA_BASE+0x114))
188 #define MACA_WARMUP ((volatile uint32_t *) (MACA_BASE+0x118))
189 #define MACA_PREAMBLE ((volatile uint32_t *) (MACA_BASE+0x11c))
190 #define MACA_WHITESEED ((volatile uint32_t *) (MACA_BASE+0x120))
191 #define MACA_FRAMESYNC0 ((volatile uint32_t *) (MACA_BASE+0x124))
192 #define MACA_FRAMESYNC1 ((volatile uint32_t *) (MACA_BASE+0x128))
193 #define MACA_TXACKDELAY ((volatile uint32_t *) (MACA_BASE+0x140))
194 #define MACA_RXACKDELAY ((volatile uint32_t *) (MACA_BASE+0x144))
195 #define MACA_EOFDELAY ((volatile uint32_t *) (MACA_BASE+0x148))
196 #define MACA_CCADELAY ((volatile uint32_t *) (MACA_BASE+0x14c))
197 #define MACA_RXEND ((volatile uint32_t *) (MACA_BASE+0x150))
198 #define MACA_TXCCADELAY ((volatile uint32_t *) (MACA_BASE+0x154))
199 #define MACA_KEY3 ((volatile uint32_t *) (MACA_BASE+0x158))
200 #define MACA_KEY2 ((volatile uint32_t *) (MACA_BASE+0x15c))
201 #define MACA_KEY1 ((volatile uint32_t *) (MACA_BASE+0x160))
202 #define MACA_KEY0 ((volatile uint32_t *) (MACA_BASE+0x164))
203 #define MACA_OPTIONS ((volatile uint32_t *) (MACA_BASE+0x180))
204 
205 
206 /******************************************************************************/
207 /* everything under this comment is messy, needs cleaning, and will */
208 /* probably change in the future */
209 /******************************************************************************/
210 
211 #define control_pre_count (7<<16) /* preamble reapeat counter */
212 #define control_rst_slot (1<<15) /* reset slot counter */
213 #define control_role (1<<13) /* set if PAN coordinator */
214 #define control_nofc (1<<12) /* set to disable FCS */
215 #define control_prm (1<<11) /* set for promiscuous mode */
216 #define control_relative (1<<10) /* 1 for relative, 0 for absolute */
217 #define control_asap (1<<9) /* 1 start now, 0 timer start */
218 #define control_bcn (1<<8) /* 1 beacon only, 0 for a */
219 #define control_auto (1<<7) /* 1 continuous rx, rx only once */
220 #define control_lfsr (1<<6) /* 1 use polynomial for Turbolink */
221 
222 #define gMACA_Clock_DIV_c 95
223 
224 //rom_base_adr equ 0x00000000 ; rom base address
225 //ram_base_adr equ 0x00400000 ; ram base address
226 //ram0_base_adr equ 0x00400000 ; ram0 base address (2K words = 8K
227 //bytes)
228 //ram1_base_adr equ 0x00402000 ; ram1 base address (6K words = 24K
229 //bytes)
230 //ram2_base_adr equ 0x00408000 ; ram2 base address (8K words = 32K
231 //bytes)
232 //ram3_base_adr equ 0x00410000 ; ram3 base address (8K words
233 enum {
234  cc_success = 0,
235  cc_timeout = 1,
236  cc_channel_busy = 2,
237  cc_crc_fail = 3,
238  cc_aborted = 4,
239  cc_no_ack = 5,
240  cc_no_data = 6,
241  cc_late_start = 7,
242  cc_ext_timeout = 8,
243  cc_ext_pnd_timeout = 9,
244  cc_nc1 = 10,
245  cc_nc2 = 11,
246  cc_nc3 = 12,
247  cc_cc_external_abort= 13,
248  cc_not_completed = 14,
249  cc_bus_error = 15
250 };
251 //control codes for mode bits
252 
253 enum {
254  control_mode_no_cca = 0,
255  control_mode_non_slotted = (1<<3),
256  control_mode_slotted = (1<<4)
257 };
258 //control codes for sequence bits
259 enum {
260  control_seq_nop = 0,
261  control_seq_abort = 1,
262  control_seq_wait = 2,
263  control_seq_tx = 3,
264  control_seq_rx = 4,
265  control_seq_txpoll = 5,
266  control_seq_cca = 6,
267  control_seq_ed = 7
268 };
269 
270 #define maca_version (*((volatile uint32_t *)(0x80004000)))
271 #define maca_reset (*((volatile uint32_t *)(0x80004004)))
272 #define maca_random (*((volatile uint32_t *)(0x80004008)))
273 #define maca_control (*((volatile uint32_t *)(0x8000400c)))
274 #define maca_status (*((volatile uint32_t *)(0x80004010)))
275 #define maca_frmpnd (*((volatile uint32_t *)(0x80004014)))
276 
277 #define maca_edvalue (*((volatile uint32_t *)(0x8000401c)))
278 #define maca_tmren (*((volatile uint32_t *)(0x80004040)))
279 #define maca_tmrdis (*((volatile uint32_t *)(0x80004044)))
280 #define maca_clk (*((volatile uint32_t *)(0x80004048)))
281 #define maca_startclk (*((volatile uint32_t *)(0x8000404c)))
282 #define maca_cplclk (*((volatile uint32_t *)(0x80004050)))
283 #define maca_sftclk (*((volatile uint32_t *)(0x80004054)))
284 #define maca_clkoffset (*((volatile uint32_t *)(0x80004058)))
285 #define maca_relclk (*((volatile uint32_t *)(0x8000405c)))
286 #define maca_cpltim (*((volatile uint32_t *)(0x80004060)))
287 #define maca_slotoffset (*((volatile uint32_t *)(0x80004064)))
288 #define maca_timestamp (*((volatile uint32_t *)(0x80004068)))
289 #define maca_dmarx (*((volatile uint32_t *)(0x80004080)))
290 #define maca_dmatx (*((volatile uint32_t *)(0x80004084)))
291 #define maca_dmatxpoll (*((volatile uint32_t *)(0x80004088)))
292 #define maca_txlen (*((volatile uint32_t *)(0x8000408c)))
293 #define maca_txseqnr (*((volatile uint32_t *)(0x80004090)))
294 #define maca_setrxlvl (*((volatile uint32_t *)(0x80004094)))
295 #define maca_getrxlvl (*((volatile uint32_t *)(0x80004098)))
296 #define maca_irq (*((volatile uint32_t *)(0x800040c0)))
297 #define maca_clrirq (*((volatile uint32_t *)(0x800040c4)))
298 #define maca_setirq (*((volatile uint32_t *)(0x800040c8)))
299 #define maca_maskirq (*((volatile uint32_t *)(0x800040cc)))
300 #define maca_panid (*((volatile uint32_t *)(0x80004100)))
301 #define maca_addr16 (*((volatile uint32_t *)(0x80004104)))
302 #define maca_maca64hi (*((volatile uint32_t *)(0x80004108)))
303 #define maca_maca64lo (*((volatile uint32_t *)(0x8000410c)))
304 #define maca_fltrej (*((volatile uint32_t *)(0x80004110)))
305 #define maca_divider (*((volatile uint32_t *)(0x80004114)))
306 #define maca_warmup (*((volatile uint32_t *)(0x80004118)))
307 #define maca_preamble (*((volatile uint32_t *)(0x8000411c)))
308 #define maca_whiteseed (*((volatile uint32_t *)(0x80004120)))
309 #define maca_framesync (*((volatile uint32_t *)(0x80004124)))
310 #define maca_framesync2 (*((volatile uint32_t *)(0x80004128)))
311 #define maca_txackdelay (*((volatile uint32_t *)(0x80004140)))
312 #define maca_rxackdelay (*((volatile uint32_t *)(0x80004144)))
313 #define maca_eofdelay (*((volatile uint32_t *)(0x80004148)))
314 #define maca_ccadelay (*((volatile uint32_t *)(0x8000414c)))
315 #define maca_rxend (*((volatile uint32_t *)(0x80004150)))
316 #define maca_txccadelay (*((volatile uint32_t *)(0x80004154)))
317 #define maca_key3 (*((volatile uint32_t *)(0x80004158)))
318 #define maca_key2 (*((volatile uint32_t *)(0x80004158)))
319 #define maca_key1 (*((volatile uint32_t *)(0x80004158)))
320 #define maca_key0 (*((volatile uint32_t *)(0x80004158)))
321 
322 
323 typedef union maca_version_reg_tag
324 {
325  struct
326  {
327  uint32_t MINOR:8;
328  uint32_t RESERVED1:8;
329  uint32_t MAJOR:8;
330  uint32_t RESERVED2:8;
331  } Bits;
332  uint32_t Reg;
333 } maca_version_reg_t;
334 
335 #define maca_version_reg_st ((maca_version_reg_t)(maca_version))
336 
337 
338 typedef union maca_reset_reg_tag
339 {
340  struct
341  {
342  uint32_t RESERVED:30;
343  uint32_t CLK_ON:1;
344  uint32_t RST:1;
345  } Bits;
346  uint32_t Reg;
347 } maca_reset_reg_t;
348 
349 #define maca_reset_reg_st ((maca_reset_reg_t)(maca_reset))
350 
351 
352 /* typedef union maca_ctrl_reg_tag */
353 /* { */
354 /* struct */
355 /* { */
356 /* uint32_t RESERVED:11; */
357 /* uint32_t ISM:1; */
358 /* uint32_t PRE_COUNT:4; */
359 /* uint32_t RSTO:1; */
360 /* uint32_t RSV:1; */
361 /* uint32_t ROLE:1; */
362 /* uint32_t NOFC:1; */
363 /* uint32_t PRM:1; */
364 /* uint32_t rel:1; */
365 /* uint32_t ASAP:1; */
366 /* uint32_t BCN:1; */
367 /* uint32_t AUTO:1; */
368 /* uint32_t LFSR:1; */
369 /* uint32_t TM:1; */
370 /* uint32_t MODE:2; */
371 /* uint32_t SEQUENCE:3; */
372 /* } Bits; */
373 /* uint32_t Reg; */
374 /* } maca_ctrl_reg_t; */
375 
376 #define maca_control_ism (1<<20)
377 #define maca_control_zigbee (~maca_control_ism)
378 
379 #define maca_ctrl_reg_st ((maca_ctrl_reg_t *)(&maca_reset))
380 #define _set_maca_test_mode(x) (maca_ctrl_reg_st->Bits.TM = x)
381 #define _set_maca_sequence(x) (maca_ctrl_reg_st->Bits.SEQUENCE = x)
382 #define _set_maca_asap(x) (maca_ctrl_reg_st->Bits.ASAP = x)
383 
384 
385 #define MACA_CTRL_ZIGBEE_MODE (0)
386 #define MACA_CTRL_ISM_MODE (1)
387 #define MACA_CTRL_PRM_NORMAL_MODE (0)
388 #define MACA_CTRL_PRM_PROMISCUOUS_MODE (1)
389 #define MACA_CTRL_BCN_ALL (0)
390 #define MACA_CTRL_BCN_BEACON (1)
391 #define MACA_CTRL_TM_NORMAL (0)
392 #define MACA_CTRL_TM_TEST (1)
393 #define MACA_CTRL_MODE_NO_CCA (0)
394 #define MACA_CTRL_MODE_NON_SLOTTED (1)
395 #define MACA_CTRL_MODE_SLOTTED (2)
396 
397 typedef enum maca_freq_chann_tag
398 {
399  SMAC_CHANN_11 = 0,
400  SMAC_CHANN_12,
401  SMAC_CHANN_13,
402  SMAC_CHANN_14,
403  SMAC_CHANN_15,
404  SMAC_CHANN_16,
405  SMAC_CHANN_17,
406  SMAC_CHANN_18,
407  SMAC_CHANN_19,
408  SMAC_CHANN_20,
409  SMAC_CHANN_21,
410  SMAC_CHANN_22,
411  SMAC_CHANN_23,
412  SMAC_CHANN_24,
413  SMAC_CHANN_25,
414  SMAC_CHANN_26,
415  MAX_SMAC_CHANNELS
416 } maca_freq_chann_t;
417 
418 
419 /* Sequence complete codes */
420 enum maca_complete_code {
421  maca_cc_success = 0,
422  maca_cc_timeout = 1,
423  maca_cc_channel_busy = 2,
424  maca_cc_crc_fail = 3,
425  maca_cc_aborted = 4,
426  maca_cc_no_ack = 5,
427  maca_cc_no_data = 6,
428  maca_cc_late_start = 7,
429  maca_cc_ext_timeout = 8,
430  maca_cc_ext_pnd_timeout = 9,
431  maca_cc_nc1 = 10,
432  maca_cc_nc2 = 11,
433  maca_cc_nc3 = 12,
434  maca_cc_cc_external_abort= 13,
435  maca_cc_not_completed = 14,
436  maca_cc_bus_error = 15
437 };
438 
439 /* control sequence codes */
440 enum maca_ctrl_seq {
441  maca_ctrl_seq_nop = 0,
442  maca_ctrl_seq_abort = 1,
443  maca_ctrl_seq_wait = 2,
444  maca_ctrl_seq_tx = 3,
445  maca_ctrl_seq_rx = 4,
446  maca_ctrl_seq_txpoll = 5,
447  maca_ctrl_seq_cca = 6,
448  maca_ctrl_seq_ed = 7
449 };
450 
451 /* transmission modes */
452 enum maca_ctrl_modes {
453  maca_ctrl_mode_no_cca = 0,
454  maca_ctrl_mode_non_slotted_csma_ca = 1,
455  maca_ctrl_mode_slotted_csma_ca = 2,
456 };
457 
458 /* MACA_CONTROL bits */
459 enum maca_ctrl_bits {
460  maca_ctrl_seq = 0, /* 3 bits */
461  maca_ctrl_mode = 3, /* 2 bits */
462  maca_ctrl_tm = 5,
463  maca_ctrl_lfsr = 6,
464  maca_ctrl_auto = 7,
465  maca_ctrl_bcn = 8,
466  maca_ctrl_asap = 9,
467  maca_ctrl_rel = 10,
468  maca_ctrl_prm = 11,
469  maca_ctrl_nofc = 12,
470  maca_ctrl_role = 13,
471  /* 14 reserved */
472  maca_ctrl_rsto = 15,
473  maca_ctrl_pre_count = 16, /* 4 bits */
474  maca_ctrl_ism = 20,
475 };
476 
477 /* MACA_IRQ bits */
478 enum maca_irqs {
479  maca_irq_acpl = 0,
480  maca_irq_poll = 1,
481  maca_irq_di = 2,
482  maca_irq_wu = 3,
483  maca_irq_rst = 4,
484  maca_irq_lvl = 9,
485  maca_irq_sftclk = 10,
486  maca_irq_flt = 11,
487  maca_irq_crc = 12,
488  maca_irq_cm = 13,
489  maca_irq_sync = 14,
490  maca_irq_strt = 15,
491 };
492 
493 /* MACA_RESET bits */
494 enum maca_reset_bits {
495  maca_reset_rst = 0,
496  maca_reset_clkon = 1,
497 };
498 
499 /* MACA_TMREN bits */
500 enum maca_tmren_bits {
501  maca_tmren_strt = 0,
502  maca_tmren_cpl = 1,
503  maca_tmren_sft = 2,
504 };
505 
506 enum maca_status_bits {
507  maca_status_ovr = 12,
508  maca_status_busy = 13,
509  maca_status_crc = 14,
510  maca_status_to = 15,
511 };
512 
513 #define action_complete_irq() bit_is_set(*MACA_IRQ,maca_irq_acpl)
514 #define filter_failed_irq() bit_is_set(*MACA_IRQ,maca_irq_flt)
515 #define checksum_failed_irq() bit_is_set(*MACA_IRQ,maca_irq_crc)
516 #define data_indication_irq() bit_is_set(*MACA_IRQ,maca_irq_di)
517 #define softclock_irq() bit_is_set(*MACA_IRQ,maca_irq_sftclk)
518 #define poll_irq() bit_is_set(*MACA_IRQ,maca_irq_poll)
519 
520 #define status_is_not_completed() ((*MACA_STATUS & 0xffff) == maca_cc_not_completed)
521 #define status_is_success() ((*MACA_STATUS & 0xffff) == maca_cc_success)
522 
523 #define SMAC_MACA_CNTL_INIT_STATE ( control_prm | control_nofc | control_mode_non_slotted )
524 
525 #define MACA_WRITE(reg, src) (reg = src)
526 #define MACA_READ(reg) reg
527 
528 #endif // _MACA_H_
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