Contiki 2.5
tmr.h
1 /*
2  * Copyright (c) 2010, Mariano Alvira <mar@devl.org> and other contributors
3  * to the MC1322x project (http://mc1322x.devl.org)
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  * notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the distribution.
14  * 3. Neither the name of the Institute nor the names of its contributors
15  * may be used to endorse or promote products derived from this software
16  * without specific prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28  * SUCH DAMAGE.
29  *
30  * This file is part of libmc1322x: see http://mc1322x.devl.org
31  * for details.
32  *
33  *
34  */
35 
36 #ifndef TMR_H
37 #define TMR_H
38 
39 #include "utils.h"
40 
41 /* Timer registers are all 16-bit wide with 16-bit access only */
42 #define TMR_OFFSET (0x20)
43 #define TMR_BASE (0x80007000)
44 #define TMR0_BASE (TMR_BASE)
45 #define TMR1_BASE (TMR_BASE + TMR_OFFSET*1)
46 #define TMR2_BASE (TMR_BASE + TMR_OFFSET*2)
47 #define TMR3_BASE (TMR_BASE + TMR_OFFSET*3)
48 
49 /* Structure-based register definitions */
50 /* Example use:
51  TMR2->CTRL = 0x1234;
52  TMR2->CTRLbits = (struct TMR_CTRL) {
53  .DIR = 1,
54  .OUTPUT_MODE = 2,
55  };
56  TMR2->CTRLbits.PRIMARY_CNT_SOURCE = 3;
57 */
58 
59 struct TMR_struct {
60  uint16_t COMP1;
61  uint16_t COMP2;
62  uint16_t CAPT;
63  uint16_t LOAD;
64  uint16_t HOLD;
65  uint16_t CNTR;
66  union {
67  uint16_t CTRL;
68  struct TMR_CTRL {
69  uint16_t OUTPUT_MODE:3;
70  uint16_t CO_INIT:1;
71  uint16_t DIR:1;
72  uint16_t LENGTH:1;
73  uint16_t ONCE:1;
74  uint16_t SECONDARY_CNT_SOURCE:2;
75  uint16_t PRIMARY_CNT_SOURCE:4;
76  uint16_t COUNT_MODE:3;
77  } CTRLbits;
78  };
79  union {
80  uint16_t SCTRL;
81  struct TMR_SCTRL {
82  uint16_t OEN:1;
83  uint16_t OPS:1;
84  uint16_t FORCE:1;
85  uint16_t VAL:1;
86  uint16_t EEOF:1;
87  uint16_t MSTR:1;
88  uint16_t CAPTURE_MODE:2;
89  uint16_t INPUT:1;
90  uint16_t IPS:1;
91  uint16_t IEFIE:1;
92  uint16_t IEF:1;
93  uint16_t TOFIE:1;
94  uint16_t TOF:1;
95  uint16_t TCFIE:1;
96  uint16_t TCF:1;
97  } SCTRLbits;
98  };
99  uint16_t CMPLD1;
100  uint16_t CMPLD2;
101  union {
102  uint16_t CSCTRL;
103  struct TMR_CSCTRL {
104  uint16_t CL1:2;
105  uint16_t CL2:2;
106  uint16_t TCF1:1;
107  uint16_t TCF2:1;
108  uint16_t TCF1EN:1;
109  uint16_t TCF2EN:1;
110  uint16_t :5;
111  uint16_t FILT_EN:1;
112  uint16_t DBG_EN:2;
113  } CSCTRLbits;
114  };
115 
116  uint16_t reserved[4];
117 
118  union {
119  uint16_t ENBL;
120  struct TMR_ENBL {
121  union {
122  struct {
123  uint16_t ENBL:4;
124  };
125  struct {
126  uint16_t ENBL3:1;
127  uint16_t ENBL2:1;
128  uint16_t ENBL1:1;
129  uint16_t ENBL0:1;
130  };
131  };
132  uint16_t :12;
133  } ENBLbits;
134  };
135 };
136 
137 static volatile struct TMR_struct * const TMR0 = (void *) (TMR0_BASE);
138 static volatile struct TMR_struct * const TMR1 = (void *) (TMR1_BASE);
139 static volatile struct TMR_struct * const TMR2 = (void *) (TMR2_BASE);
140 static volatile struct TMR_struct * const TMR3 = (void *) (TMR3_BASE);
141 
142 /* Get timer pointer from timer number */
143 #define TMR_ADDR(x) ((volatile struct TMR_struct *)(((uint32_t)(x) * TMR_OFFSET) + TMR_BASE))
144 
145 /* Get timer number from the timer pointer. */
146 #define TMR_NUM(x) (((uint32_t)(x) - TMR_BASE) / TMR_OFFSET)
147 
148 /* Used to compute which enable bit to set for a particular timer, e.g.
149  TMR0.ENBL |= TMR_ENABLE_BIT(TMR2);
150  Helpful when you're using macros to define timers
151 */
152 #define TMR_ENABLE_BIT(x) (1 << TMR_NUM(x))
153 
154 #define TMR0_PIN GPIO_08
155 #define TMR1_PIN GPIO_09
156 #define TMR2_PIN GPIO_10
157 #define TMR3_PIN GPIO_11
158 
159 /* Old timer definitions, for compatibility */
160 #ifndef REG_NO_COMPAT
161 
162 #define TMR_REGOFF_COMP1 (0x0)
163 #define TMR_REGOFF_COMP2 (0x2)
164 #define TMR_REGOFF_CAPT (0x4)
165 #define TMR_REGOFF_LOAD (0x6)
166 #define TMR_REGOFF_HOLD (0x8)
167 #define TMR_REGOFF_CNTR (0xa)
168 #define TMR_REGOFF_CTRL (0xc)
169 #define TMR_REGOFF_SCTRL (0xe)
170 #define TMR_REGOFF_CMPLD1 (0x10)
171 #define TMR_REGOFF_CMPLD2 (0x12)
172 #define TMR_REGOFF_CSCTRL (0x14)
173 #define TMR_REGOFF_ENBL (0x1e)
174 
175 /* one enable register to rule them all */
176 #define TMR_ENBL ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_ENBL))
177 
178 /* Timer 0 registers */
179 #define TMR0_COMP1 ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_COMP1))
180 #define TMR0_COMP_UP TMR0_COMP1
181 #define TMR0_COMP2 ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_COMP2))
182 #define TMR0_COMP_DOWN TMR0_COMP2
183 #define TMR0_CAPT ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_CAPT))
184 #define TMR0_LOAD ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_LOAD))
185 #define TMR0_HOLD ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_HOLD))
186 #define TMR0_CNTR ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_CNTR))
187 #define TMR0_CTRL ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_CTRL))
188 #define TMR0_SCTRL ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_SCTRL))
189 #define TMR0_CMPLD1 ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_CMPLD1))
190 #define TMR0_CMPLD2 ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_CMPLD2))
191 #define TMR0_CSCTRL ((volatile uint16_t *) (TMR0_BASE + TMR_REGOFF_CSCTRL))
192 
193 /* Timer 1 registers */
194 #define TMR1_COMP1 ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_COMP1))
195 #define TMR1_COMP_UP TMR1_COMP1
196 #define TMR1_COMP2 ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_COMP2))
197 #define TMR1_COMP_DOWN TMR1_COMP2
198 #define TMR1_CAPT ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_CAPT))
199 #define TMR1_LOAD ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_LOAD))
200 #define TMR1_HOLD ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_HOLD))
201 #define TMR1_CNTR ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_CNTR))
202 #define TMR1_CTRL ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_CTRL))
203 #define TMR1_SCTRL ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_SCTRL))
204 #define TMR1_CMPLD1 ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_CMPLD1))
205 #define TMR1_CMPLD2 ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_CMPLD2))
206 #define TMR1_CSCTRL ((volatile uint16_t *) (TMR1_BASE + TMR_REGOFF_CSCTRL))
207 
208 /* Timer 2 registers */
209 #define TMR2_COMP1 ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_COMP1))
210 #define TMR2_COMP_UP TMR2_COMP1
211 #define TMR2_COMP2 ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_COMP2))
212 #define TMR2_COMP_DOWN TMR2_COMP2
213 #define TMR2_CAPT ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_CAPT))
214 #define TMR2_LOAD ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_LOAD))
215 #define TMR2_HOLD ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_HOLD))
216 #define TMR2_CNTR ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_CNTR))
217 #define TMR2_CTRL ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_CTRL))
218 #define TMR2_SCTRL ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_SCTRL))
219 #define TMR2_CMPLD1 ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_CMPLD1))
220 #define TMR2_CMPLD2 ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_CMPLD2))
221 #define TMR2_CSCTRL ((volatile uint16_t *) (TMR2_BASE + TMR_REGOFF_CSCTRL))
222 
223 /* Timer 3 registers */
224 #define TMR3_COMP1 ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_COMP1))
225 #define TMR3_COMP_UP TMR3_COMP1
226 #define TMR3_COMP2 ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_COMP2))
227 #define TMR3_COMP_DOWN TMR3_COMP2
228 #define TMR3_CAPT ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_CAPT))
229 #define TMR3_LOAD ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_LOAD))
230 #define TMR3_HOLD ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_HOLD))
231 #define TMR3_CNTR ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_CNTR))
232 #define TMR3_CTRL ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_CTRL))
233 #define TMR3_SCTRL ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_SCTRL))
234 #define TMR3_CMPLD1 ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_CMPLD1))
235 #define TMR3_CMPLD2 ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_CMPLD2))
236 #define TMR3_CSCTRL ((volatile uint16_t *) (TMR3_BASE + TMR_REGOFF_CSCTRL))
237 
238 #define TMR(num, reg) CAT2(TMR,num,_##reg)
239 
240 #endif /* REG_NO_COMPAT */
241 
242 /* Initialize timer. This just counts and interrupts, doesn't drive an output.
243  timer_num = 0, 1, 2, 3
244  rate = desired rate in Hz,
245  enable_int = whether to enable an interrupt on every cycle
246  Returns actual timer rate. */
247 uint32_t timer_setup_ex(int timer_num, uint32_t rate, int enable_int);
248 
249 /* Initialize timer. This just counts and interrupts, doesn't drive an output.
250  timer = TMR0, TMR1, TMR2, TMR3
251  rate = desired rate in Hz,
252  enable_int = whether to enable an interrupt on every cycle
253  Returns actual timer rate. */
254 #define timer_setup(timer,rate,enable_int) timer_setup_ex(TMR_NUM(timer), rate, enable_int)
255 
256 #endif
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