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platform-conf.h
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1 /*
2  * Copyright (c) 2010, Swedish Institute of Computer Science.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
12  * documentation and/or other materials provided with the distribution.
13  * 3. Neither the name of the Institute nor the names of its contributors
14  * may be used to endorse or promote products derived from this software
15  * without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27  * SUCH DAMAGE.
28  *
29  * $Id: platform-conf.h,v 1.2 2010/12/16 22:52:27 adamdunkels Exp $
30  */
31 
32 /**
33  * \file
34  * A brief description of what this file is
35  * \author
36  * Niclas Finne <nfi@sics.se>
37  * Joakim Eriksson <joakime@sics.se>
38  */
39 
40 #ifndef __PLATFORM_CONF_H__
41 #define __PLATFORM_CONF_H__
42 
43 /*
44  * Definitions below are dictated by the hardware and not really
45  * changeable!
46  */
47 /* Platform TMOTE_SKY */
48 #define TMOTE_SKY 1
49 
50 #define PLATFORM_HAS_LEDS 1
51 #define PLATFORM_HAS_BUTTON 1
52 
53 #ifdef __IAR_SYSTEMS_ICC__
54 #define __MSP430F1611__ 1
55 #define __MSP430__ 1
56 #define CC_CONF_INLINE
57 #define BV(x) (1 << x)
58 #else
59 #define CC_CONF_INLINE inline
60 #define MSP430_MEMCPY_WORKAROUND 1
61 #endif
62 
63 
64 /* CPU target speed in Hz */
65 #define F_CPU 3900000uL /*2457600uL*/
66 
67 /* Our clock resolution, this is the same as Unix HZ. */
68 #define CLOCK_CONF_SECOND 128UL
69 
70 #define BAUD2UBR(baud) ((F_CPU/baud))
71 
72 #define CCIF
73 #define CLIF
74 
75 #define HAVE_STDINT_H
76 #include "msp430def.h"
77 
78 
79 /* Types for clocks and uip_stats */
80 typedef unsigned short uip_stats_t;
81 typedef unsigned long clock_time_t;
82 typedef unsigned long off_t;
83 
84 /* the low-level radio driver */
85 #define NETSTACK_CONF_RADIO cc2420_driver
86 
87 /* LED ports */
88 #define LEDS_PxDIR P5DIR
89 #define LEDS_PxOUT P5OUT
90 #define LEDS_CONF_RED 0x10
91 #define LEDS_CONF_GREEN 0x20
92 #define LEDS_CONF_YELLOW 0x40
93 
94 /* DCO speed resynchronization for more robust UART, etc. */
95 #ifndef DCOSYNCH_CONF_ENABLED
96 #define DCOSYNCH_CONF_ENABLED 1
97 #endif /* DCOSYNCH_CONF_ENABLED */
98 #ifndef DCOSYNCH_CONF_PERIOD
99 #define DCOSYNCH_CONF_PERIOD 30
100 #endif /* DCOSYNCH_CONF_PERIOD */
101 
102 #define ROM_ERASE_UNIT_SIZE 512
103 #define XMEM_ERASE_UNIT_SIZE (64*1024L)
104 
105 
106 #define CFS_CONF_OFFSET_TYPE long
107 
108 
109 /* Use the first 64k of external flash for node configuration */
110 #define NODE_ID_XMEM_OFFSET (0 * XMEM_ERASE_UNIT_SIZE)
111 
112 /* Use the second 64k of external flash for codeprop. */
113 #define EEPROMFS_ADDR_CODEPROP (1 * XMEM_ERASE_UNIT_SIZE)
114 
115 #define CFS_XMEM_CONF_OFFSET (2 * XMEM_ERASE_UNIT_SIZE)
116 #define CFS_XMEM_CONF_SIZE (1 * XMEM_ERASE_UNIT_SIZE)
117 
118 #define CFS_RAM_CONF_SIZE 4096
119 
120 /*
121  * SPI bus configuration for the TMote Sky.
122  */
123 
124 /* SPI input/output registers. */
125 #define SPI_TXBUF U0TXBUF
126 #define SPI_RXBUF U0RXBUF
127 
128  /* USART0 Tx ready? */
129 #define SPI_WAITFOREOTx() while ((U0TCTL & TXEPT) == 0)
130  /* USART0 Rx ready? */
131 #define SPI_WAITFOREORx() while ((IFG1 & URXIFG0) == 0)
132  /* USART0 Tx buffer ready? */
133 #define SPI_WAITFORTxREADY() while ((IFG1 & UTXIFG0) == 0)
134 
135 #define SCK 1 /* P3.1 - Output: SPI Serial Clock (SCLK) */
136 #define MOSI 2 /* P3.2 - Output: SPI Master out - slave in (MOSI) */
137 #define MISO 3 /* P3.3 - Input: SPI Master in - slave out (MISO) */
138 
139 /*
140  * SPI bus - M25P80 external flash configuration.
141  */
142 
143 #define FLASH_PWR 3 /* P4.3 Output */
144 #define FLASH_CS 4 /* P4.4 Output */
145 #define FLASH_HOLD 7 /* P4.7 Output */
146 
147 /* Enable/disable flash access to the SPI bus (active low). */
148 
149 #define SPI_FLASH_ENABLE() ( P4OUT &= ~BV(FLASH_CS) )
150 #define SPI_FLASH_DISABLE() ( P4OUT |= BV(FLASH_CS) )
151 
152 #define SPI_FLASH_HOLD() ( P4OUT &= ~BV(FLASH_HOLD) )
153 #define SPI_FLASH_UNHOLD() ( P4OUT |= BV(FLASH_HOLD) )
154 
155 /*
156  * SPI bus - CC2420 pin configuration.
157  */
158 
159 #define CC2420_CONF_SYMBOL_LOOP_COUNT 800
160 
161 /* P1.0 - Input: FIFOP from CC2420 */
162 #define CC2420_FIFOP_PORT(type) P1##type
163 #define CC2420_FIFOP_PIN 0
164 /* P1.3 - Input: FIFO from CC2420 */
165 #define CC2420_FIFO_PORT(type) P1##type
166 #define CC2420_FIFO_PIN 3
167 /* P1.4 - Input: CCA from CC2420 */
168 #define CC2420_CCA_PORT(type) P1##type
169 #define CC2420_CCA_PIN 4
170 /* P4.1 - Input: SFD from CC2420 */
171 #define CC2420_SFD_PORT(type) P4##type
172 #define CC2420_SFD_PIN 1
173 /* P4.2 - Output: SPI Chip Select (CS_N) */
174 #define CC2420_CSN_PORT(type) P4##type
175 #define CC2420_CSN_PIN 2
176 /* P4.5 - Output: VREG_EN to CC2420 */
177 #define CC2420_VREG_PORT(type) P4##type
178 #define CC2420_VREG_PIN 5
179 /* P4.6 - Output: RESET_N to CC2420 */
180 #define CC2420_RESET_PORT(type) P4##type
181 #define CC2420_RESET_PIN 6
182 
183 #define CC2420_IRQ_VECTOR PORT1_VECTOR
184 
185 /* Pin status. */
186 #define CC2420_FIFOP_IS_1 (!!(CC2420_FIFOP_PORT(IN) & BV(CC2420_FIFOP_PIN)))
187 #define CC2420_FIFO_IS_1 (!!(CC2420_FIFO_PORT(IN) & BV(CC2420_FIFO_PIN)))
188 #define CC2420_CCA_IS_1 (!!(CC2420_CCA_PORT(IN) & BV(CC2420_CCA_PIN)))
189 #define CC2420_SFD_IS_1 (!!(CC2420_SFD_PORT(IN) & BV(CC2420_SFD_PIN)))
190 
191 /* The CC2420 reset pin. */
192 #define SET_RESET_INACTIVE() (CC2420_RESET_PORT(OUT) |= BV(CC2420_RESET_PIN))
193 #define SET_RESET_ACTIVE() (CC2420_RESET_PORT(OUT) &= ~BV(CC2420_RESET_PIN))
194 
195 /* CC2420 voltage regulator enable pin. */
196 #define SET_VREG_ACTIVE() (CC2420_VREG_PORT(OUT) |= BV(CC2420_VREG_PIN))
197 #define SET_VREG_INACTIVE() (CC2420_VREG_PORT(OUT) &= ~BV(CC2420_VREG_PIN))
198 
199 /* CC2420 rising edge trigger for external interrupt 0 (FIFOP). */
200 #define CC2420_FIFOP_INT_INIT() do { \
201  CC2420_FIFOP_PORT(IES) &= ~BV(CC2420_FIFOP_PIN); \
202  CC2420_CLEAR_FIFOP_INT(); \
203  } while(0)
204 
205 /* FIFOP on external interrupt 0. */
206 #define CC2420_ENABLE_FIFOP_INT() do {CC2420_FIFOP_PORT(IE) |= BV(CC2420_FIFOP_PIN);} while(0)
207 #define CC2420_DISABLE_FIFOP_INT() do {CC2420_FIFOP_PORT(IE) &= ~BV(CC2420_FIFOP_PIN);} while(0)
208 #define CC2420_CLEAR_FIFOP_INT() do {CC2420_FIFOP_PORT(IFG) &= ~BV(CC2420_FIFOP_PIN);} while(0)
209 
210 /*
211  * Enables/disables CC2420 access to the SPI bus (not the bus).
212  * (Chip Select)
213  */
214 
215  /* ENABLE CSn (active low) */
216 #define CC2420_SPI_ENABLE() (CC2420_CSN_PORT(OUT) &= ~BV(CC2420_CSN_PIN))
217  /* DISABLE CSn (active low) */
218 #define CC2420_SPI_DISABLE() (CC2420_CSN_PORT(OUT) |= BV(CC2420_CSN_PIN))
219 #define CC2420_SPI_IS_ENABLED() ((CC2420_CSN_PORT(OUT) & BV(CC2420_CSN_PIN)) != BV(CC2420_CSN_PIN))
220 
221 #endif /* __PLATFORM_CONF_H__ */
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