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platform-conf.h
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1 /*
2  * Copyright (c) 2010, Swedish Institute of Computer Science.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
12  * documentation and/or other materials provided with the distribution.
13  * 3. Neither the name of the Institute nor the names of its contributors
14  * may be used to endorse or promote products derived from this software
15  * without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27  * SUCH DAMAGE.
28  *
29  * $Id: platform-conf.h,v 1.1 2010/08/24 16:26:38 joxe Exp $
30  */
31 
32 /**
33  * \file
34  * A brief description of what this file is
35  * \author
36  * Joakim Eriksson <joakime@sics.se>
37  */
38 
39 #ifndef __PLATFORM_CONF_H__
40 #define __PLATFORM_CONF_H__
41 
42 /*
43  * Definitions below are dictated by the hardware and not really
44  * changeable!
45  */
46 #define ZOLERTIA_Z1 0 /* Enric */
47 #define ZOLERTIA_Z1SP 1 /* Enric */
48 
49 /* CPU target speed in Hz */
50 /* CPU target speed in Hz */
51 #define F_CPU 8000000uL // 8MHz by default
52 //Enric #define F_CPU 3900000uL /*2457600uL*/
53 
54 /* Our clock resolution, this is the same as Unix HZ. */
55 #define CLOCK_CONF_SECOND 128UL
56 
57 #define BAUD2UBR(baud) ((F_CPU/baud))
58 
59 #define CCIF
60 #define CLIF
61 
62 #define CC_CONF_INLINE inline
63 
64 #define HAVE_STDINT_H
65 #define MSP430_MEMCPY_WORKAROUND 1
66 #include "msp430def.h"
67 
68 
69 /* Types for clocks and uip_stats */
70 typedef unsigned short uip_stats_t;
71 typedef unsigned long clock_time_t;
72 typedef unsigned long off_t;
73 
74 /* the low-level radio driver */
75 #define NETSTACK_CONF_RADIO cc2420_driver
76 
77 /*
78  * Definitions below are dictated by the hardware and not really
79  * changeable!
80  */
81 
82 /* LED ports */
83 #define LEDS_PxDIR P4DIR
84 #define LEDS_PxOUT P4OUT
85 #define LEDS_CONF_RED 0x04
86 #define LEDS_CONF_GREEN 0x01
87 #define LEDS_CONF_YELLOW 0x80
88 
89 /* DCO speed resynchronization for more robust UART, etc. */
90 #define DCOSYNCH_CONF_ENABLED 0
91 #define DCOSYNCH_CONF_PERIOD 30
92 
93 #define ROM_ERASE_UNIT_SIZE 512
94 #define XMEM_ERASE_UNIT_SIZE (64*1024L)
95 
96 
97 #define CFS_CONF_OFFSET_TYPE long
98 
99 /* Use the first 64k of external flash for node configuration */
100 #define NODE_ID_XMEM_OFFSET (0 * XMEM_ERASE_UNIT_SIZE)
101 
102 /* Use the second 64k of external flash for codeprop. */
103 #define EEPROMFS_ADDR_CODEPROP (1 * XMEM_ERASE_UNIT_SIZE)
104 
105 #define CFS_XMEM_CONF_OFFSET (2 * XMEM_ERASE_UNIT_SIZE)
106 #define CFS_XMEM_CONF_SIZE (1 * XMEM_ERASE_UNIT_SIZE)
107 
108 #define CFS_RAM_CONF_SIZE 4096
109 
110 /*
111  * SPI bus configuration for the TMote Sky.
112  */
113 
114 /* SPI input/output registers. */
115 #define SPI_TXBUF UCB0TXBUF
116 #define SPI_RXBUF UCB0RXBUF
117 
118  /* USART0 Tx ready? */
119 #define SPI_WAITFOREOTx() while ((UCB0STAT & UCBUSY) != 0)
120  /* USART0 Rx ready? */
121 #define SPI_WAITFOREORx() while ((IFG2 & UCB0RXIFG) == 0)
122  /* USART0 Tx buffer ready? */
123 #define SPI_WAITFORTxREADY() while ((IFG2 & UCB0TXIFG) == 0)
124 
125 #define MOSI 1 /* P3.1 - Output: SPI Master out - slave in (MOSI) */
126 #define MISO 2 /* P3.2 - Input: SPI Master in - slave out (MISO) */
127 #define SCK 3 /* P3.3 - Output: SPI Serial Clock (SCLK) */
128 
129 /*
130  * SPI bus - M25P80 external flash configuration.
131  */
132 //#define FLASH_PWR 3 /* P4.3 Output */ ALWAYS POWERED ON Z1
133 #define FLASH_CS 4 /* P4.4 Output */
134 #define FLASH_HOLD 7 /* P5.7 Output */
135 
136 /* Enable/disable flash access to the SPI bus (active low). */
137 
138 #define SPI_FLASH_ENABLE() ( P4OUT &= ~BV(FLASH_CS) )
139 #define SPI_FLASH_DISABLE() ( P4OUT |= BV(FLASH_CS) )
140 
141 #define SPI_FLASH_HOLD() ( P5OUT &= ~BV(FLASH_HOLD) )
142 #define SPI_FLASH_UNHOLD() ( P5OUT |= BV(FLASH_HOLD) )
143 
144 
145 /*
146  * SPI bus - CC2420 pin configuration.
147  */
148 
149 #define CC2420_CONF_SYMBOL_LOOP_COUNT 1302 /* 326us msp430X @ 8MHz */
150 
151 /* P1.2 - Input: FIFOP from CC2420 */
152 #define CC2420_FIFOP_PORT(type) P1##type
153 #define CC2420_FIFOP_PIN 2
154 /* P1.3 - Input: FIFO from CC2420 */
155 #define CC2420_FIFO_PORT(type) P1##type
156 #define CC2420_FIFO_PIN 3
157 /* P1.4 - Input: CCA from CC2420 */
158 #define CC2420_CCA_PORT(type) P1##type
159 #define CC2420_CCA_PIN 4
160 /* P4.1 - Input: SFD from CC2420 */
161 #define CC2420_SFD_PORT(type) P4##type
162 #define CC2420_SFD_PIN 1
163  /* P3.0 - Output: SPI Chip Select (CS_N) */
164 #define CC2420_CSN_PORT(type) P3##type
165 #define CC2420_CSN_PIN 0
166 /* P4.5 - Output: VREG_EN to CC2420 */
167 #define CC2420_VREG_PORT(type) P4##type
168 #define CC2420_VREG_PIN 5
169 /* P4.6 - Output: RESET_N to CC2420 */
170 #define CC2420_RESET_PORT(type) P4##type
171 #define CC2420_RESET_PIN 6
172 
173 
174 #define CC2420_IRQ_VECTOR PORT1_VECTOR
175 
176 /* Pin status. */
177 #define CC2420_FIFOP_IS_1 (!!(CC2420_FIFOP_PORT(IN) & BV(CC2420_FIFOP_PIN)))
178 #define CC2420_FIFO_IS_1 (!!(CC2420_FIFO_PORT(IN) & BV(CC2420_FIFO_PIN)))
179 #define CC2420_CCA_IS_1 (!!(CC2420_CCA_PORT(IN) & BV(CC2420_CCA_PIN)))
180 #define CC2420_SFD_IS_1 (!!(CC2420_SFD_PORT(IN) & BV(CC2420_SFD_PIN)))
181 
182 /* The CC2420 reset pin. */
183 #define SET_RESET_INACTIVE() (CC2420_RESET_PORT(OUT) |= BV(CC2420_RESET_PIN))
184 #define SET_RESET_ACTIVE() (CC2420_RESET_PORT(OUT) &= ~BV(CC2420_RESET_PIN))
185 
186 /* CC2420 voltage regulator enable pin. */
187 #define SET_VREG_ACTIVE() (CC2420_VREG_PORT(OUT) |= BV(CC2420_VREG_PIN))
188 #define SET_VREG_INACTIVE() (CC2420_VREG_PORT(OUT) &= ~BV(CC2420_VREG_PIN))
189 
190 /* CC2420 rising edge trigger for external interrupt 0 (FIFOP). */
191 #define CC2420_FIFOP_INT_INIT() do { \
192  CC2420_FIFOP_PORT(IES) &= ~BV(CC2420_FIFOP_PIN); \
193  CC2420_CLEAR_FIFOP_INT(); \
194  } while(0)
195 
196 /* FIFOP on external interrupt 0. */
197 #define CC2420_ENABLE_FIFOP_INT() do {CC2420_FIFOP_PORT(IE) |= BV(CC2420_FIFOP_PIN);} while(0)
198 #define CC2420_DISABLE_FIFOP_INT() do {CC2420_FIFOP_PORT(IE) &= ~BV(CC2420_FIFOP_PIN);} while(0)
199 #define CC2420_CLEAR_FIFOP_INT() do {CC2420_FIFOP_PORT(IFG) &= ~BV(CC2420_FIFOP_PIN);} while(0)
200 
201 /*
202  * Enables/disables CC2420 access to the SPI bus (not the bus).
203  * (Chip Select)
204  */
205 
206  /* ENABLE CSn (active low) */
207 #define CC2420_SPI_ENABLE() (CC2420_CSN_PORT(OUT) &= ~BV(CC2420_CSN_PIN))
208  /* DISABLE CSn (active low) */
209 #define CC2420_SPI_DISABLE() (CC2420_CSN_PORT(OUT) |= BV(CC2420_CSN_PIN))
210 #define CC2420_SPI_IS_ENABLED() ((CC2420_CSN_PORT(OUT) & BV(CC2420_CSN_PIN)) != BV(CC2420_CSN_PIN))
211 
212 #endif /* __PLATFORM_CONF_H__ */
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