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platform-jcreate-conf.h
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1 /*
2  * Copyright (c) 2011, Swedish Institute of Computer Science.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
12  * documentation and/or other materials provided with the distribution.
13  * 3. Neither the name of the Institute nor the names of its contributors
14  * may be used to endorse or promote products derived from this software
15  * without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27  * SUCH DAMAGE.
28  */
29 
30 /**
31  * \file
32  * Platform configuration for the Sentilla JCreate
33  * \author
34  * Niclas Finne <nfi@sics.se>
35  * Joakim Eriksson <joakime@sics.se>
36  */
37 
38 #ifndef __PLATFORM_CONF_H__
39 #define __PLATFORM_CONF_H__
40 
41 /*
42  * Definitions below are dictated by the hardware and not really
43  * changeable!
44  */
45 /* Platform TMOTE_SKY */
46 #define TMOTE_SKY 1
47 
48 #define LEDS_CONF_ALL 255
49 #define PLATFORM_HAS_LEDS 1
50 #define PLATFORM_HAS_BUTTON 0
51 
52 /* CPU target speed in Hz */
53 #define F_CPU 3900000uL /*2457600uL*/
54 
55 /* Our clock resolution, this is the same as Unix HZ. */
56 #define CLOCK_CONF_SECOND 128UL
57 
58 #define BAUD2UBR(baud) ((F_CPU/baud))
59 
60 #define CCIF
61 #define CLIF
62 
63 #define CC_CONF_INLINE inline
64 
65 #define HAVE_STDINT_H
66 #define MSP430_MEMCPY_WORKAROUND 1
67 #include "msp430def.h"
68 
69 
70 /* Types for clocks and uip_stats */
71 typedef unsigned short uip_stats_t;
72 typedef unsigned long clock_time_t;
73 typedef unsigned long off_t;
74 
75 /* the low-level radio driver */
76 #define NETSTACK_CONF_RADIO cc2420_driver
77 
78 /* LED ports */
79 #define LEDS_PxDIR P5DIR
80 #define LEDS_PxOUT P5OUT
81 #define LEDS_CONF_RED 0x10
82 #define LEDS_CONF_GREEN 0x20
83 #define LEDS_CONF_YELLOW 0x40
84 
85 /* DCO speed resynchronization for more robust UART, etc. */
86 #ifndef DCOSYNCH_CONF_ENABLED
87 #define DCOSYNCH_CONF_ENABLED 1
88 #endif /* DCOSYNCH_CONF_ENABLED */
89 #ifndef DCOSYNCH_CONF_PERIOD
90 #define DCOSYNCH_CONF_PERIOD 30
91 #endif /* DCOSYNCH_CONF_PERIOD */
92 
93 #define ROM_ERASE_UNIT_SIZE 512
94 #define XMEM_ERASE_UNIT_SIZE (64*1024L)
95 
96 
97 #define CFS_CONF_OFFSET_TYPE long
98 
99 
100 /* Use the first 64k of external flash for node configuration */
101 #define NODE_ID_XMEM_OFFSET (0 * XMEM_ERASE_UNIT_SIZE)
102 
103 /* Use the second 64k of external flash for codeprop. */
104 #define EEPROMFS_ADDR_CODEPROP (1 * XMEM_ERASE_UNIT_SIZE)
105 
106 #define CFS_XMEM_CONF_OFFSET (2 * XMEM_ERASE_UNIT_SIZE)
107 #define CFS_XMEM_CONF_SIZE (1 * XMEM_ERASE_UNIT_SIZE)
108 
109 #define CFS_RAM_CONF_SIZE 4096
110 
111 /*
112  * SPI bus configuration for the TMote Sky.
113  */
114 
115 /* SPI input/output registers. */
116 #define SPI_TXBUF U0TXBUF
117 #define SPI_RXBUF U0RXBUF
118 
119  /* USART0 Tx ready? */
120 #define SPI_WAITFOREOTx() while ((U0TCTL & TXEPT) == 0)
121  /* USART0 Rx ready? */
122 #define SPI_WAITFOREORx() while ((IFG1 & URXIFG0) == 0)
123  /* USART0 Tx buffer ready? */
124 #define SPI_WAITFORTxREADY() while ((IFG1 & UTXIFG0) == 0)
125 
126 #define SCK 1 /* P3.1 - Output: SPI Serial Clock (SCLK) */
127 #define MOSI 2 /* P3.2 - Output: SPI Master out - slave in (MOSI) */
128 #define MISO 3 /* P3.3 - Input: SPI Master in - slave out (MISO) */
129 
130 /*
131  * SPI bus - M25P80 external flash configuration.
132  */
133 
134 #define FLASH_PWR 3 /* P4.3 Output */
135 #define FLASH_CS 4 /* P4.4 Output */
136 #define FLASH_HOLD 7 /* P4.7 Output */
137 
138 /* Enable/disable flash access to the SPI bus (active low). */
139 
140 #define SPI_FLASH_ENABLE() ( P4OUT &= ~BV(FLASH_CS) )
141 #define SPI_FLASH_DISABLE() ( P4OUT |= BV(FLASH_CS) )
142 
143 #define SPI_FLASH_HOLD() ( P4OUT &= ~BV(FLASH_HOLD) )
144 #define SPI_FLASH_UNHOLD() ( P4OUT |= BV(FLASH_HOLD) )
145 
146 /*
147  * SPI bus - CC2420 pin configuration.
148  */
149 
150 #define CC2420_CONF_SYMBOL_LOOP_COUNT 800
151 
152 /* P1.0 - Input: FIFOP from CC2420 */
153 #define CC2420_FIFOP_PORT(type) P1##type
154 #define CC2420_FIFOP_PIN 0
155 /* P1.3 - Input: FIFO from CC2420 */
156 #define CC2420_FIFO_PORT(type) P1##type
157 #define CC2420_FIFO_PIN 3
158 /* P1.4 - Input: CCA from CC2420 */
159 #define CC2420_CCA_PORT(type) P1##type
160 #define CC2420_CCA_PIN 4
161 /* P4.1 - Input: SFD from CC2420 */
162 #define CC2420_SFD_PORT(type) P4##type
163 #define CC2420_SFD_PIN 1
164 /* P4.2 - Output: SPI Chip Select (CS_N) */
165 #define CC2420_CSN_PORT(type) P4##type
166 #define CC2420_CSN_PIN 2
167 /* P4.5 - Output: VREG_EN to CC2420 */
168 #define CC2420_VREG_PORT(type) P4##type
169 #define CC2420_VREG_PIN 5
170 /* P4.6 - Output: RESET_N to CC2420 */
171 #define CC2420_RESET_PORT(type) P4##type
172 #define CC2420_RESET_PIN 6
173 
174 #define CC2420_IRQ_VECTOR PORT1_VECTOR
175 
176 /* Pin status. */
177 #define CC2420_FIFOP_IS_1 (!!(CC2420_FIFOP_PORT(IN) & BV(CC2420_FIFOP_PIN)))
178 #define CC2420_FIFO_IS_1 (!!(CC2420_FIFO_PORT(IN) & BV(CC2420_FIFO_PIN)))
179 #define CC2420_CCA_IS_1 (!!(CC2420_CCA_PORT(IN) & BV(CC2420_CCA_PIN)))
180 #define CC2420_SFD_IS_1 (!!(CC2420_SFD_PORT(IN) & BV(CC2420_SFD_PIN)))
181 
182 /* The CC2420 reset pin. */
183 #define SET_RESET_INACTIVE() (CC2420_RESET_PORT(OUT) |= BV(CC2420_RESET_PIN))
184 #define SET_RESET_ACTIVE() (CC2420_RESET_PORT(OUT) &= ~BV(CC2420_RESET_PIN))
185 
186 /* CC2420 voltage regulator enable pin. */
187 #define SET_VREG_ACTIVE() (CC2420_VREG_PORT(OUT) |= BV(CC2420_VREG_PIN))
188 #define SET_VREG_INACTIVE() (CC2420_VREG_PORT(OUT) &= ~BV(CC2420_VREG_PIN))
189 
190 /* CC2420 rising edge trigger for external interrupt 0 (FIFOP). */
191 #define CC2420_FIFOP_INT_INIT() do { \
192  CC2420_FIFOP_PORT(IES) &= ~BV(CC2420_FIFOP_PIN); \
193  CC2420_CLEAR_FIFOP_INT(); \
194  } while(0)
195 
196 /* FIFOP on external interrupt 0. */
197 #define CC2420_ENABLE_FIFOP_INT() do {CC2420_FIFOP_PORT(IE) |= BV(CC2420_FIFOP_PIN);} while(0)
198 #define CC2420_DISABLE_FIFOP_INT() do {CC2420_FIFOP_PORT(IE) &= ~BV(CC2420_FIFOP_PIN);} while(0)
199 #define CC2420_CLEAR_FIFOP_INT() do {CC2420_FIFOP_PORT(IFG) &= ~BV(CC2420_FIFOP_PIN);} while(0)
200 
201 /*
202  * Enables/disables CC2420 access to the SPI bus (not the bus).
203  * (Chip Select)
204  */
205 
206  /* ENABLE CSn (active low) */
207 #define CC2420_SPI_ENABLE() (CC2420_CSN_PORT(OUT) &= ~BV(CC2420_CSN_PIN))
208  /* DISABLE CSn (active low) */
209 #define CC2420_SPI_DISABLE() (CC2420_CSN_PORT(OUT) |= BV(CC2420_CSN_PIN))
210 #define CC2420_SPI_IS_ENABLED() ((CC2420_CSN_PORT(OUT) & BV(CC2420_CSN_PIN)) != BV(CC2420_CSN_PIN))
211 
212 #endif /* __PLATFORM_CONF_H__ */
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