Contiki 2.5
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This file contains the register definitions for the AT86RF230. More...
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Macros | |
#define | RG_TRX_STATUS (0x01) |
Offset for register TRX_STATUS. | |
#define | SR_CCA_DONE 0x01, 0x80, 7 |
Access parameters for sub-register CCA_DONE in register RG_TRX_STATUS. | |
#define | SR_CCA_STATUS 0x01, 0x40, 6 |
Access parameters for sub-register CCA_STATUS in register RG_TRX_STATUS. | |
#define | SR_TRX_STATUS 0x01, 0x1f, 0 |
Access parameters for sub-register TRX_STATUS in register RG_TRX_STATUS. | |
#define | P_ON (0) |
Constant P_ON for sub-register SR_TRX_STATUS. | |
#define | BUSY_RX (1) |
Constant BUSY_RX for sub-register SR_TRX_STATUS. | |
#define | BUSY_TX (2) |
Constant BUSY_TX for sub-register SR_TRX_STATUS. | |
#define | RX_ON (6) |
Constant RX_ON for sub-register SR_TRX_STATUS. | |
#define | TRX_OFF (8) |
Constant TRX_OFF for sub-register SR_TRX_STATUS. | |
#define | PLL_ON (9) |
Constant PLL_ON for sub-register SR_TRX_STATUS. | |
#define | SLEEP (15) |
Constant SLEEP for sub-register SR_TRX_STATUS. | |
#define | BUSY_RX_AACK (17) |
Constant BUSY_RX_AACK for sub-register SR_TRX_STATUS. | |
#define | BUSY_TX_ARET (18) |
Constant BUSY_TX_ARET for sub-register SR_TRX_STATUS. | |
#define | RX_AACK_ON (22) |
Constant RX_AACK_ON for sub-register SR_TRX_STATUS. | |
#define | TX_ARET_ON (25) |
Constant TX_ARET_ON for sub-register SR_TRX_STATUS. | |
#define | RX_ON_NOCLK (28) |
Constant RX_ON_NOCLK for sub-register SR_TRX_STATUS. | |
#define | RX_AACK_ON_NOCLK (29) |
Constant RX_AACK_ON_NOCLK for sub-register SR_TRX_STATUS. | |
#define | BUSY_RX_AACK_NOCLK (30) |
Constant BUSY_RX_AACK_NOCLK for sub-register SR_TRX_STATUS. | |
#define | RG_TRX_STATE (0x02) |
Offset for register TRX_STATE. | |
#define | SR_TRAC_STATUS 0x02, 0xe0, 5 |
Access parameters for sub-register TRAC_STATUS in register RG_TRX_STATE. | |
#define | SR_TRX_CMD 0x02, 0x1f, 0 |
Access parameters for sub-register TRX_CMD in register RG_TRX_STATE. | |
#define | CMD_NOP (0) |
Constant CMD_NOP for sub-register SR_TRX_CMD. | |
#define | CMD_TX_START (2) |
Constant CMD_TX_START for sub-register SR_TRX_CMD. | |
#define | CMD_FORCE_TRX_OFF (3) |
Constant CMD_FORCE_TRX_OFF for sub-register SR_TRX_CMD. | |
#define | CMD_RX_ON (6) |
Constant CMD_RX_ON for sub-register SR_TRX_CMD. | |
#define | CMD_TRX_OFF (8) |
Constant CMD_TRX_OFF for sub-register SR_TRX_CMD. | |
#define | CMD_PLL_ON (9) |
Constant CMD_PLL_ON for sub-register SR_TRX_CMD. | |
#define | CMD_RX_AACK_ON (22) |
Constant CMD_RX_AACK_ON for sub-register SR_TRX_CMD. | |
#define | CMD_TX_ARET_ON (25) |
Constant CMD_TX_ARET_ON for sub-register SR_TRX_CMD. | |
#define | RG_TRX_CTRL_0 (0x03) |
Offset for register TRX_CTRL_0. | |
#define | RG_TRX_CTRL_1 (0x04) |
Offset for register TRX_CTRL_1. | |
#define | SR_PAD_IO 0x03, 0xc0, 6 |
Access parameters for sub-register PAD_IO in register RG_TRX_CTRL_0. | |
#define | SR_PAD_IO_CLKM 0x03, 0x30, 4 |
Access parameters for sub-register PAD_IO_CLKM in register RG_TRX_CTRL_0. | |
#define | CLKM_2mA (0) |
Constant CLKM_2mA for sub-register SR_PAD_IO_CLKM. | |
#define | CLKM_4mA (1) |
Constant CLKM_4mA for sub-register SR_PAD_IO_CLKM. | |
#define | CLKM_6mA (2) |
Constant CLKM_6mA for sub-register SR_PAD_IO_CLKM. | |
#define | CLKM_8mA (3) |
Constant CLKM_8mA for sub-register SR_PAD_IO_CLKM. | |
#define | SR_CLKM_SHA_SEL 0x03, 0x08, 3 |
Access parameters for sub-register CLKM_SHA_SEL in register RG_TRX_CTRL_0. | |
#define | SR_CLKM_CTRL 0x03, 0x07, 0 |
Access parameters for sub-register CLKM_CTRL in register RG_TRX_CTRL_0. | |
#define | CLKM_no_clock (0) |
Constant CLKM_no_clock for sub-register SR_CLKM_CTRL. | |
#define | CLKM_1MHz (1) |
Constant CLKM_1MHz for sub-register SR_CLKM_CTRL. | |
#define | CLKM_2MHz (2) |
Constant CLKM_2MHz for sub-register SR_CLKM_CTRL. | |
#define | CLKM_4MHz (3) |
Constant CLKM_4MHz for sub-register SR_CLKM_CTRL. | |
#define | CLKM_8MHz (4) |
Constant CLKM_8MHz for sub-register SR_CLKM_CTRL. | |
#define | CLKM_16MHz (5) |
Constant CLKM_16MHz for sub-register SR_CLKM_CTRL. | |
#define | RG_PHY_TX_PWR (0x05) |
Offset for register PHY_TX_PWR. | |
#define | SR_TX_AUTO_CRC_ON 0x05, 0x80, 7 |
Access parameters for sub-register TX_AUTO_CRC_ON in register RG_PHY_TX_PWR. | |
#define | SR_TX_PWR 0x05, 0x0f, 0 |
Access parameters for sub-register TX_PWR in register RG_PHY_TX_PWR. | |
#define | RG_PHY_RSSI (0x06) |
Offset for register PHY_RSSI. | |
#define | SR_RSSI 0x06, 0x1f, 0 |
Access parameters for sub-register RSSI in register RG_PHY_RSSI. | |
#define | RG_PHY_ED_LEVEL (0x07) |
Offset for register PHY_ED_LEVEL. | |
#define | SR_ED_LEVEL 0x07, 0xff, 0 |
Access parameters for sub-register ED_LEVEL in register RG_PHY_ED_LEVEL. | |
#define | RG_PHY_CC_CCA (0x08) |
Offset for register PHY_CC_CCA. | |
#define | SR_CCA_REQUEST 0x08, 0x80, 7 |
Access parameters for sub-register CCA_REQUEST in register RG_PHY_CC_CCA. | |
#define | SR_CCA_MODE 0x08, 0x60, 5 |
Access parameters for sub-register CCA_MODE in register RG_PHY_CC_CCA. | |
#define | SR_CHANNEL 0x08, 0x1f, 0 |
Access parameters for sub-register CHANNEL in register RG_PHY_CC_CCA. | |
#define | RG_CCA_THRES (0x09) |
Offset for register CCA_THRES. | |
#define | SR_CCA_CS_THRES 0x09, 0xf0, 4 |
Access parameters for sub-register CCA_CS_THRES in register RG_CCA_THRES. | |
#define | SR_CCA_ED_THRES 0x09, 0x0f, 0 |
Access parameters for sub-register CCA_ED_THRES in register RG_CCA_THRES. | |
#define | RG_IRQ_MASK (0x0e) |
Offset for register IRQ_MASK. | |
#define | SR_IRQ_MASK 0x0e, 0xff, 0 |
Access parameters for sub-register IRQ_MASK in register RG_IRQ_MASK. | |
#define | RG_IRQ_STATUS (0x0f) |
Offset for register IRQ_STATUS. | |
#define | SR_IRQ_7_BAT_LOW 0x0f, 0x80, 7 |
Access parameters for sub-register IRQ_7_BAT_LOW in register RG_IRQ_STATUS. | |
#define | SR_IRQ_6_TRX_UR 0x0f, 0x40, 6 |
Access parameters for sub-register IRQ_6_TRX_UR in register RG_IRQ_STATUS. | |
#define | SR_IRQ_5 0x0f, 0x20, 5 |
Access parameters for sub-register IRQ_5 in register RG_IRQ_STATUS. | |
#define | SR_IRQ_4 0x0f, 0x10, 4 |
Access parameters for sub-register IRQ_4 in register RG_IRQ_STATUS. | |
#define | SR_IRQ_3_TRX_END 0x0f, 0x08, 3 |
Access parameters for sub-register IRQ_3_TRX_END in register RG_IRQ_STATUS. | |
#define | SR_IRQ_2_RX_START 0x0f, 0x04, 2 |
Access parameters for sub-register IRQ_2_RX_START in register RG_IRQ_STATUS. | |
#define | SR_IRQ_1_PLL_UNLOCK 0x0f, 0x02, 1 |
Access parameters for sub-register IRQ_1_PLL_UNLOCK in register RG_IRQ_STATUS. | |
#define | SR_IRQ_0_PLL_LOCK 0x0f, 0x01, 0 |
Access parameters for sub-register IRQ_0_PLL_LOCK in register RG_IRQ_STATUS. | |
#define | RG_VREG_CTRL (0x10) |
Offset for register VREG_CTRL. | |
#define | SR_AVREG_EXT 0x10, 0x80, 7 |
Access parameters for sub-register AVREG_EXT in register RG_VREG_CTRL. | |
#define | SR_AVDD_OK 0x10, 0x40, 6 |
Access parameters for sub-register AVDD_OK in register RG_VREG_CTRL. | |
#define | SR_AVREG_TRIM 0x10, 0x30, 4 |
Access parameters for sub-register AVREG_TRIM in register RG_VREG_CTRL. | |
#define | AVREG_1_80V (0) |
Constant AVREG_1_80V for sub-register SR_AVREG_TRIM. | |
#define | AVREG_1_75V (1) |
Constant AVREG_1_75V for sub-register SR_AVREG_TRIM. | |
#define | AVREG_1_84V (2) |
Constant AVREG_1_84V for sub-register SR_AVREG_TRIM. | |
#define | AVREG_1_88V (3) |
Constant AVREG_1_88V for sub-register SR_AVREG_TRIM. | |
#define | SR_DVREG_EXT 0x10, 0x08, 3 |
Access parameters for sub-register DVREG_EXT in register RG_VREG_CTRL. | |
#define | SR_DVDD_OK 0x10, 0x04, 2 |
Access parameters for sub-register DVDD_OK in register RG_VREG_CTRL. | |
#define | SR_DVREG_TRIM 0x10, 0x03, 0 |
Access parameters for sub-register DVREG_TRIM in register RG_VREG_CTRL. | |
#define | DVREG_1_80V (0) |
Constant DVREG_1_80V for sub-register SR_DVREG_TRIM. | |
#define | DVREG_1_75V (1) |
Constant DVREG_1_75V for sub-register SR_DVREG_TRIM. | |
#define | DVREG_1_84V (2) |
Constant DVREG_1_84V for sub-register SR_DVREG_TRIM. | |
#define | DVREG_1_88V (3) |
Constant DVREG_1_88V for sub-register SR_DVREG_TRIM. | |
#define | RG_BATMON (0x11) |
Offset for register BATMON. | |
#define | SR_BATMON_OK 0x11, 0x20, 5 |
Access parameters for sub-register BATMON_OK in register RG_BATMON. | |
#define | SR_BATMON_HR 0x11, 0x10, 4 |
Access parameters for sub-register BATMON_HR in register RG_BATMON. | |
#define | SR_BATMON_VTH 0x11, 0x0f, 0 |
Access parameters for sub-register BATMON_VTH in register RG_BATMON. | |
#define | RG_XOSC_CTRL (0x12) |
Offset for register XOSC_CTRL. | |
#define | RG_RX_SYN 0x15 |
Offset for register RX_SYN. | |
#define | RG_XAH_CTRL_1 0x17 |
Offset for register XAH_CTRL_1. | |
#define | SR_XTAL_MODE 0x12, 0xf0, 4 |
Access parameters for sub-register XTAL_MODE in register RG_XOSC_CTRL. | |
#define | SR_XTAL_TRIM 0x12, 0x0f, 0 |
Access parameters for sub-register XTAL_TRIM in register RG_XOSC_CTRL. | |
#define | RG_FTN_CTRL (0x18) |
Offset for register FTN_CTRL. | |
#define | SR_FTN_START 0x18, 0x80, 7 |
Access parameters for sub-register FTN_START in register RG_FTN_CTRL. | |
#define | SR_FTNV 0x18, 0x3f, 0 |
Access parameters for sub-register FTNV in register RG_FTN_CTRL. | |
#define | RG_PLL_CF (0x1a) |
Offset for register PLL_CF. | |
#define | SR_PLL_CF_START 0x1a, 0x80, 7 |
Access parameters for sub-register PLL_CF_START in register RG_PLL_CF. | |
#define | SR_PLL_CF 0x1a, 0x0f, 0 |
Access parameters for sub-register PLL_CF in register RG_PLL_CF. | |
#define | RG_PLL_DCU (0x1b) |
Offset for register PLL_DCU. | |
#define | SR_PLL_DCU_START 0x1b, 0x80, 7 |
Access parameters for sub-register PLL_DCU_START in register RG_PLL_DCU. | |
#define | SR_PLL_DCUW 0x1b, 0x3f, 0 |
Access parameters for sub-register PLL_DCUW in register RG_PLL_DCU. | |
#define | RG_PART_NUM (0x1c) |
Offset for register PART_NUM. | |
#define | SR_PART_NUM 0x1c, 0xff, 0 |
Access parameters for sub-register PART_NUM in register RG_PART_NUM. | |
#define | RF230 (2) |
Constant RF230 for sub-register SR_PART_NUM. | |
#define | RG_VERSION_NUM (0x1d) |
Offset for register VERSION_NUM. | |
#define | SR_VERSION_NUM 0x1d, 0xff, 0 |
Access parameters for sub-register VERSION_NUM in register RG_VERSION_NUM. | |
#define | RG_MAN_ID_0 (0x1e) |
Offset for register MAN_ID_0. | |
#define | SR_MAN_ID_0 0x1e, 0xff, 0 |
Access parameters for sub-register MAN_ID_0 in register RG_MAN_ID_0. | |
#define | RG_MAN_ID_1 (0x1f) |
Offset for register MAN_ID_1. | |
#define | SR_MAN_ID_1 0x1f, 0xff, 0 |
Access parameters for sub-register MAN_ID_1 in register RG_MAN_ID_1. | |
#define | RG_SHORT_ADDR_0 (0x20) |
Offset for register SHORT_ADDR_0. | |
#define | SR_SHORT_ADDR_0 0x20, 0xff, 0 |
Access parameters for sub-register SHORT_ADDR_0 in register RG_SHORT_ADDR_0. | |
#define | RG_SHORT_ADDR_1 (0x21) |
Offset for register SHORT_ADDR_1. | |
#define | SR_SHORT_ADDR_1 0x21, 0xff, 0 |
Access parameters for sub-register SHORT_ADDR_1 in register RG_SHORT_ADDR_1. | |
#define | RG_PAN_ID_0 (0x22) |
Offset for register PAN_ID_0. | |
#define | SR_PAN_ID_0 0x22, 0xff, 0 |
Access parameters for sub-register PAN_ID_0 in register RG_PAN_ID_0. | |
#define | RG_PAN_ID_1 (0x23) |
Offset for register PAN_ID_1. | |
#define | SR_PAN_ID_1 0x23, 0xff, 0 |
Access parameters for sub-register PAN_ID_1 in register RG_PAN_ID_1. | |
#define | RG_IEEE_ADDR_0 (0x24) |
Offset for register IEEE_ADDR_0. | |
#define | SR_IEEE_ADDR_0 0x24, 0xff, 0 |
Access parameters for sub-register IEEE_ADDR_0 in register RG_IEEE_ADDR_0. | |
#define | RG_IEEE_ADDR_1 (0x25) |
Offset for register IEEE_ADDR_1. | |
#define | SR_IEEE_ADDR_1 0x25, 0xff, 0 |
Access parameters for sub-register IEEE_ADDR_1 in register RG_IEEE_ADDR_1. | |
#define | RG_IEEE_ADDR_2 (0x26) |
Offset for register IEEE_ADDR_2. | |
#define | SR_IEEE_ADDR_2 0x26, 0xff, 0 |
Access parameters for sub-register IEEE_ADDR_2 in register RG_IEEE_ADDR_2. | |
#define | RG_IEEE_ADDR_3 (0x27) |
Offset for register IEEE_ADDR_3. | |
#define | SR_IEEE_ADDR_3 0x27, 0xff, 0 |
Access parameters for sub-register IEEE_ADDR_3 in register RG_IEEE_ADDR_3. | |
#define | RG_IEEE_ADDR_4 (0x28) |
Offset for register IEEE_ADDR_4. | |
#define | SR_IEEE_ADDR_4 0x28, 0xff, 0 |
Access parameters for sub-register IEEE_ADDR_4 in register RG_IEEE_ADDR_4. | |
#define | RG_IEEE_ADDR_5 (0x29) |
Offset for register IEEE_ADDR_5. | |
#define | SR_IEEE_ADDR_5 0x29, 0xff, 0 |
Access parameters for sub-register IEEE_ADDR_5 in register RG_IEEE_ADDR_5. | |
#define | RG_IEEE_ADDR_6 (0x2a) |
Offset for register IEEE_ADDR_6. | |
#define | SR_IEEE_ADDR_6 0x2a, 0xff, 0 |
Access parameters for sub-register IEEE_ADDR_6 in register RG_IEEE_ADDR_6. | |
#define | RG_IEEE_ADDR_7 (0x2b) |
Offset for register IEEE_ADDR_7. | |
#define | SR_IEEE_ADDR_7 0x2b, 0xff, 0 |
Access parameters for sub-register IEEE_ADDR_7 in register RG_IEEE_ADDR_7. | |
#define | RG_XAH_CTRL_0 (0x2c) |
Offset for register XAH_CTRL. | |
#define | SR_MAX_FRAME_RETRIES 0x2c, 0xf0, 4 |
Access parameters for sub-register MAX_FRAME_RETRIES in register RG_XAH_CTRL_0. | |
#define | SR_MAX_CSMA_RETRIES 0x2c, 0x0e, 1 |
Access parameters for sub-register MAX_CSMA_RETRIES in register RG_XAH_CTRL_0. | |
#define | RG_CSMA_SEED_0 (0x2d) |
Offset for register CSMA_SEED_0. | |
#define | SR_CSMA_SEED_0 0x2d, 0xff, 0 |
Access parameters for sub-register CSMA_SEED_0 in register RG_CSMA_SEED_0. | |
#define | RG_CSMA_SEED_1 (0x2e) |
Offset for register CSMA_SEED_1. | |
#define | RG_CSMA_BE 0x2f |
Offset for register CSMA_BE. | |
#define | SR_MIN_BE 0x2e, 0xc0, 6 |
Access parameters for sub-register MIN_BE in register RG_CSMA_SEED_1. | |
#define | SR_I_AM_COORD 0x2e, 0x08, 3 |
Access parameters for sub-register I_AM_COORD in register RG_CSMA_SEED_1. | |
#define | SR_CSMA_SEED_1 0x2e, 0x07, 0 |
Access parameters for sub-register CSMA_SEED_1 in register RG_CSMA_SEED_1. | |
This file contains the register definitions for the AT86RF230.
Definition in file at86rf230_registermap.h.